| Message ID | 20231215141832.9492-4-roger.pau@citrix.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | x86/iommu: improve setup time of hwdom IOMMU | expand |
On 15.12.2023 15:18, Roger Pau Monne wrote: > However take into account the minimum number of levels required by unity maps > when setting the page table levels. > > The previous setting of the page table levels for PV guests based on the > highest RAM address was bogus, as there can be other non-RAM regions past the > highest RAM address that need to be mapped, for example device MMIO. > > For HVM we also take amd_iommu_min_paging_mode into account, however if unity > maps require more than 4 levels attempting to add those will currently fail at > the p2m level, as 4 levels is the maximum supported. > > Fixes: 0700c962ac2d ('Add AMD IOMMU support into hypervisor') > Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> with one remark: > --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c > +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c > @@ -359,21 +359,17 @@ int __read_mostly amd_iommu_min_paging_mode = 1; > static int cf_check amd_iommu_domain_init(struct domain *d) > { > struct domain_iommu *hd = dom_iommu(d); > + int pglvl = amd_iommu_get_paging_mode( > + PFN_DOWN(1UL << domain_max_paddr_bits(d))); This would feel safer as 1UL << (domain_max_paddr_bits(d) - PAGE_SHIFT) as then not being prone to UB should the function ever become capable of returning 64. Jan
diff --git a/xen/drivers/passthrough/amd/pci_amd_iommu.c b/xen/drivers/passthrough/amd/pci_amd_iommu.c index 6bc73dc21052..cc3e2ccd5ed7 100644 --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -359,21 +359,17 @@ int __read_mostly amd_iommu_min_paging_mode = 1; static int cf_check amd_iommu_domain_init(struct domain *d) { struct domain_iommu *hd = dom_iommu(d); + int pglvl = amd_iommu_get_paging_mode( + PFN_DOWN(1UL << domain_max_paddr_bits(d))); + + if ( pglvl < 0 ) + return pglvl; /* - * Choose the number of levels for the IOMMU page tables. - * - PV needs 3 or 4, depending on whether there is RAM (including hotplug - * RAM) above the 512G boundary. - * - HVM could in principle use 3 or 4 depending on how much guest - * physical address space we give it, but this isn't known yet so use 4 - * unilaterally. - * - Unity maps may require an even higher number. + * Choose the number of levels for the IOMMU page tables, taking into + * account unity maps. */ - hd->arch.amd.paging_mode = max(amd_iommu_get_paging_mode( - is_hvm_domain(d) - ? 1UL << (DEFAULT_DOMAIN_ADDRESS_WIDTH - PAGE_SHIFT) - : get_upper_mfn_bound() + 1), - amd_iommu_min_paging_mode); + hd->arch.amd.paging_mode = max(pglvl, amd_iommu_min_paging_mode); return 0; }
However take into account the minimum number of levels required by unity maps when setting the page table levels. The previous setting of the page table levels for PV guests based on the highest RAM address was bogus, as there can be other non-RAM regions past the highest RAM address that need to be mapped, for example device MMIO. For HVM we also take amd_iommu_min_paging_mode into account, however if unity maps require more than 4 levels attempting to add those will currently fail at the p2m level, as 4 levels is the maximum supported. Fixes: 0700c962ac2d ('Add AMD IOMMU support into hypervisor') Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> --- Changes since v2: - Use the renamed domain_max_paddr_bits(). Changes since v1: - Use paging_max_paddr_bits() instead of hardcoding DEFAULT_DOMAIN_ADDRESS_WIDTH. --- xen/drivers/passthrough/amd/pci_amd_iommu.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-)