@@ -533,9 +533,30 @@ static void cf_check init_intel(struct cpuinfo_x86 *c)
init_intel_cacheinfo(c);
if (c->cpuid_level > 9) {
unsigned eax = cpuid_eax(10);
+ unsigned int cnt = (eax >> 8) & 0xff;
+
/* Check for version and the number of counters */
- if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
+ if ((eax & 0xff) && cnt && (cnt <= 32)) {
+ uint64_t global_ctrl;
+ unsigned int cnt_mask = (1UL << cnt) - 1;
+
+ /*
+ * On (some?) Sapphire/Emerald Rapids platforms each
+ * package-BSP starts with all the enable bits for the
+ * general-purpose PMCs cleared. Adjust so counters
+ * can be enabled from EVNTSEL.
+ */
+ rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, global_ctrl);
+ if ((global_ctrl & cnt_mask) != cnt_mask) {
+ printk("CPU%u: invalid PERF_GLOBAL_CTRL: %#"
+ PRIx64 " adjusting to %#" PRIx64 "\n",
+ smp_processor_id(), global_ctrl,
+ global_ctrl | cnt_mask);
+ wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
+ global_ctrl | cnt_mask);
+ }
__set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
+ }
}
if ( !cpu_has(c, X86_FEATURE_XTOPOLOGY) )
When Architectural Performance Monitoring is available, the PERF_GLOBAL_CTRL MSR contains per-counter enable bits that is ANDed with the enable bit in the counter EVNTSEL MSR in order for a PMC counter to be enabled. So far the watchdog code seems to have relied on the PERF_GLOBAL_CTRL enable bits being set by default, but at least on some Intel Sapphire and Emerald Rapids this is no longer the case, and Xen reports: Testing NMI watchdog on all CPUs: 0 40 stuck The first CPU on each package is started with PERF_GLOBAL_CTRL zeroed, so PMC0 doesn't start counting when the enable bit in EVNTSEL0 is set, due to the relevant enable bit in PERF_GLOBAL_CTRL not being set. Check and adjust PERF_GLOBAL_CTRL during CPU initialization so that all the general-purpose PMCs are enabled. Doing so brings the state of the package-BSP PERF_GLOBAL_CTRL in line with the rest of the CPUs on the system. While there also adjust the check for ARCH_PERFMON in order to require a single counter to be present instead of two. Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> --- Changes since v2: - Print message on invalid PERF_GLOBAL_CTRL. - Use a mask instead of type truncation. - Adjust the check to require a single counter instead of 2. Changes since v1: - Do the adjustment of PERF_GLOBAL_CTRL even if the watchdog is not used, and enable all counters. --- xen/arch/x86/cpu/intel.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)