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pr=C From: Michal Orzel To: CC: Michal Orzel , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu Subject: [PATCH] SUPPORT.md: clarify support of booting 32-bit Xen on ARMv8 Date: Thu, 29 Feb 2024 13:13:52 +0100 Message-ID: <20240229121352.11264-1-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636E:EE_|SA3PR12MB7950:EE_ X-MS-Office365-Filtering-Correlation-Id: 2915a05b-b973-4cee-05e5-08dc391fe8e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 15x22nPmqGnGVLv2hFZ9761BTe3iGCjzUF/OyawdJnP/7OAoC8k0Xi09erYYUlC6Y1ISUE1KEcSYh42KbXsBCYcEV0ZbwW7c99L0O9xwspuJ8RRYZRgiNeA1VgfXgVWikYCvdzzVJgvrKwIY5K4pAuyonmluSPMxmsuYVKgPohsYRGnIt+0yCPd5BJkPHMW680D0ItLUKD7tSzF4sFgRDYlRUFJeVJwPXj0YbA81eGOZpbOYaKmTMZiCUvHGmwAVw1+t8coIoX1F0SUa2BBB0EZ3nMqjJamT9jc4LIXhwHfiBRS9GpeDkzOO4Sc5VHBBNh3V3+I+EvhKK6U5A8Whe9Y9u++RB5+QRuqhDjK/Dv4I5pdhI7l+oPQZW+7P2+1aqrnDT9bXuazYVI3swTGkUq40XxeX5A6FU09r6fVmwZl3mKCNpkYaFQrfTeNRMYBj+6x2TnonNmYP1XvoLlzEVON+fo/UsVZjpZsltm3Rwqg76+UrdMwjVP6tstzFBWtgMSI/Ay8UjNr7NVJc0w3o17hVnp1QLPftqQhtyQx7prceaFHi1Mpz6KTJOjQUREvOPxYTzNLLbxeJJAvzkPJ0EzMLkL/j35r4q++JbYxDUOjIlFqA3t4qpChezSPEvK7hMZW1nW5CxrKVxjDGwPVmDc/Z14FDC6Y2iIWmpbwVZMBPnAH0m2HYg25qFwXXDzsFpnTAn3knzQvaP0AXW/2qdpGqUoy/+vyn0tegEWx2FEqI0nJcaLVmC2pI7v2iwbyL X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(36860700004)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Feb 2024 12:13:59.3432 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2915a05b-b973-4cee-05e5-08dc391fe8e8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7950 Since commit bd1001db0af1 ("xen/arm: arm32: Allow Xen to boot on unidentified CPUs"), it's been possible to boot 32-bit Xen on ARMv8A CPUs in AArch32 state (assuming HW supports EL2 execution in AArch32). Clarify the support statement and mark it as Tech Preview, as this use case is uncommon and hasn't really been tested/hardened. Signed-off-by: Michal Orzel Acked-by: Julien Grall --- SUPPORT.md | 1 + 1 file changed, 1 insertion(+) diff --git a/SUPPORT.md b/SUPPORT.md index a90d1108c9d9..acc61230bb5e 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -40,6 +40,7 @@ supported in this document. Status: Supported Status, Cortex A57 r0p0-r1p1: Supported, not security supported Status, Cortex A77 r0p0-r1p0: Supported, not security supported + Status, Xen in AArch32 mode: Tech Preview For the Cortex A57 r0p0 - r1p1, see Errata 832075. For the Cortex A77 r0p0 - r1p0, see Errata 1508412.