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[155.185.85.8]) by smtp.gmail.com with ESMTPSA id en6-20020a17090728c600b00a465a012cf1sm1621493ejc.18.2024.03.15.03.59.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Mar 2024 03:59:38 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1ea15f2e-e2bb-11ee-afdd-a90da7624cb6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=minervasys-tech.20230601.gappssmtp.com; s=20230601; t=1710500378; x=1711105178; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x7qgLspBNpxBucIcCqnnYGElw1yQeDssnQnTybbfdgM=; b=n/N0OpmmGWYcWTTGlmIRya2J/ahuYyh8HR4n51Q1P0Qz+5+q8RKZuZWSkYhAD1dG3x JbEST+310zrvbVfa8dY3cLhIk+h/tV1pe/jsDYZWxKOSR/FAl2KmNCUaedLkcnjDcJ0E oztL9kJCXIvO6KzY8HOkknx9EZu6AYU1sG0nUJFVnzBPRZQu2aWy60LA9IlT7y3T+Ej6 iqQNJkbjpoN7//aC2lWlfZ1I9030EK52+qjxnZgUaEuaZ5vKvEGb0NSkYCEE4kETAQ/z VLgZLRT+Vzsy3ZTAT2xAItEIntI5i4wcROlk6y1t5NZCwW6zbifLfuE/rbiEOCoMHFy9 lNEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710500378; x=1711105178; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x7qgLspBNpxBucIcCqnnYGElw1yQeDssnQnTybbfdgM=; b=a3A3sAhnejEfeg3B4FoEG4vm/k7SJFLI1VVJ2T+n7xX51ZqN4STjwDvmn/RUpUmAB2 9zmWeKl2s4t2b9SslQ/uwDVX+MVCckH+cF004k05jNc5o84ce+rOA0lD6z8pFJCl8Ju6 l2ea6davXjfSoOanByE4z8FoKy1KbVMjgGJ2hzpL9onoTlDhjAwF6crli2we6xFj9nty wyP9S6kAyMC2hHx2ZesRkVc7OPM040eotMkaiZCg1VtavJFSz7ZvjhPr4uvIBCi/u+qA 4o81iZpsB0htuRk+VVJrzPHgOg/J5emIBf0THB1iYqsxrPVn32CQeYoEnegkPilgtEoa e2GA== X-Gm-Message-State: AOJu0YygWMV/G1rAKVeEoMDVIpmEXoq/XGlnpGIP/5m9luvhqJlRijWl wOzyWta0d0G/PkkrxEpQJSjMTm7F4xOyD4p57KumtTcMpe3gLDZsRabqF5l4XQSXSUjT9aTt9Kr DCM0= X-Google-Smtp-Source: AGHT+IGx2+970rAP4gkHNMJwtJTjBvh81JAADd4udQI1aCReWCaMxMdvAxC3x2LRrXqZsfP9RkGCmA== X-Received: by 2002:a17:906:aad1:b0:a46:966b:ebfe with SMTP id kt17-20020a170906aad100b00a46966bebfemr326115ejb.46.1710500378562; Fri, 15 Mar 2024 03:59:38 -0700 (PDT) From: Carlo Nonato To: xen-devel@lists.xenproject.org Cc: Carlo Nonato , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Marco Solieri Subject: [PATCH v7 02/14] xen/arm: add initial support for LLC coloring on arm64 Date: Fri, 15 Mar 2024 11:58:50 +0100 Message-Id: <20240315105902.160047-3-carlo.nonato@minervasys.tech> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240315105902.160047-1-carlo.nonato@minervasys.tech> References: <20240315105902.160047-1-carlo.nonato@minervasys.tech> MIME-Version: 1.0 LLC coloring needs to know the last level cache layout in order to make the best use of it. This can be probed by inspecting the CLIDR_EL1 register, so the Last Level is defined as the last level visible by this register. Note that this excludes system caches in some platforms. Static memory allocation and cache coloring are incompatible because static memory can't be guaranteed to use only colors assigned to the domain. Panic during DomUs creation when both are enabled. Based on original work from: Luca Miccio Signed-off-by: Carlo Nonato Signed-off-by: Marco Solieri --- v7: - only minor changes v6: - get_llc_way_size() now checks for at least separate I/D caches v5: - used - instead of _ for filenames - moved static-mem check in this patch - moved dom0 colors parsing in next patch - moved color allocation and configuration in next patch - moved check_colors() in next patch - colors are now printed in short form v4: - added "llc-coloring" cmdline option for the boot-time switch - dom0 colors are now checked during domain init as for any other domain - fixed processor.h masks bit width - check for overflow in parse_color_config() - check_colors() now checks also that colors are sorted and unique --- docs/misc/cache-coloring.rst | 14 ++++++ xen/arch/arm/Kconfig | 1 + xen/arch/arm/Makefile | 1 + xen/arch/arm/dom0less-build.c | 6 +++ xen/arch/arm/include/asm/processor.h | 16 ++++++ xen/arch/arm/llc-coloring.c | 75 ++++++++++++++++++++++++++++ xen/arch/arm/setup.c | 3 ++ xen/common/llc-coloring.c | 2 +- xen/include/xen/llc-coloring.h | 4 ++ 9 files changed, 121 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/llc-coloring.c diff --git a/docs/misc/cache-coloring.rst b/docs/misc/cache-coloring.rst index 52ce52ffbd..871e7a3ddb 100644 --- a/docs/misc/cache-coloring.rst +++ b/docs/misc/cache-coloring.rst @@ -120,6 +120,20 @@ Auto-probing of LLC specs LLC size and number of ways are probed automatically by default. +In the Arm implementation, this is done by inspecting the CLIDR_EL1 register. +This means that other system caches that aren't visible there are ignored. + LLC specs can be manually set via the above command line parameters. This bypasses any auto-probing and it's used to overcome failing situations or for debugging/testing purposes. + +Known issues and limitations +**************************** + +"xen,static-mem" isn't supported when coloring is enabled +######################################################### + +In the domain configuration, "xen,static-mem" allows memory to be statically +allocated to the domain. This isn't possible when LLC coloring is enabled, +because that memory can't be guaranteed to use only colors assigned to the +domain. diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 40f834bb71..fa96d8247e 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -8,6 +8,7 @@ config ARM_64 depends on !ARM_32 select 64BIT select HAS_FAST_MULTIPLY + select HAS_LLC_COLORING config ARM def_bool y diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 7b1350e2ef..18ae566521 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_IOREQ_SERVER) += ioreq.o obj-y += irq.o obj-y += kernel.init.o obj-$(CONFIG_LIVEPATCH) += livepatch.o +obj-$(CONFIG_LLC_COLORING) += llc-coloring.o obj-y += mem_access.o obj-y += mm.o obj-y += monitor.o diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index fb63ec6fd1..1142f7f74a 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -879,7 +880,12 @@ void __init create_domUs(void) panic("No more domain IDs available\n"); if ( dt_find_property(node, "xen,static-mem", NULL) ) + { + if ( llc_coloring_enabled ) + panic("LLC coloring and static memory are incompatible\n"); + flags |= CDF_staticmem; + } if ( dt_property_read_bool(node, "direct-map") ) { diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/asm/processor.h index 8e02410465..ef33ea198c 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -18,6 +18,22 @@ #define CTR_IDC_SHIFT 28 #define CTR_DIC_SHIFT 29 +/* CCSIDR Current Cache Size ID Register */ +#define CCSIDR_LINESIZE_MASK _AC(0x7, UL) +#define CCSIDR_NUMSETS_SHIFT 13 +#define CCSIDR_NUMSETS_MASK _AC(0x3fff, UL) +#define CCSIDR_NUMSETS_SHIFT_FEAT_CCIDX 32 +#define CCSIDR_NUMSETS_MASK_FEAT_CCIDX _AC(0xffffff, UL) + +/* CSSELR Cache Size Selection Register */ +#define CSSELR_LEVEL_MASK _AC(0x7, UL) +#define CSSELR_LEVEL_SHIFT 1 + +/* CLIDR Cache Level ID Register */ +#define CLIDR_CTYPEn_SHIFT(n) (3 * ((n) - 1)) +#define CLIDR_CTYPEn_MASK _AC(0x7, UL) +#define CLIDR_CTYPEn_LEVELS 7 + #define ICACHE_POLICY_VPIPT 0 #define ICACHE_POLICY_AIVIVT 1 #define ICACHE_POLICY_VIPT 2 diff --git a/xen/arch/arm/llc-coloring.c b/xen/arch/arm/llc-coloring.c new file mode 100644 index 0000000000..b83540ff41 --- /dev/null +++ b/xen/arch/arm/llc-coloring.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Last Level Cache (LLC) coloring support for ARM + * + * Copyright (C) 2022 Xilinx Inc. + */ +#include +#include + +#include +#include + +/* Return the LLC way size by probing the hardware */ +unsigned int __init get_llc_way_size(void) +{ + register_t ccsidr_el1; + register_t clidr_el1 = READ_SYSREG(CLIDR_EL1); + register_t csselr_el1 = READ_SYSREG(CSSELR_EL1); + register_t id_aa64mmfr2_el1 = READ_SYSREG(ID_AA64MMFR2_EL1); + uint32_t ccsidr_numsets_shift = CCSIDR_NUMSETS_SHIFT; + uint32_t ccsidr_numsets_mask = CCSIDR_NUMSETS_MASK; + unsigned int n, line_size, num_sets; + + for ( n = CLIDR_CTYPEn_LEVELS; n != 0; n-- ) + { + uint8_t ctype_n = (clidr_el1 >> CLIDR_CTYPEn_SHIFT(n)) & + CLIDR_CTYPEn_MASK; + + /* Unified cache (see Arm ARM DDI 0487J.a D19.2.27) */ + if ( ctype_n == 0b100 ) + break; + } + + if ( n == 0 ) + return 0; + + WRITE_SYSREG((n - 1) << CSSELR_LEVEL_SHIFT, CSSELR_EL1); + isb(); + + ccsidr_el1 = READ_SYSREG(CCSIDR_EL1); + + /* Arm ARM: (Log2(Number of bytes in cache line)) - 4 */ + line_size = 1U << ((ccsidr_el1 & CCSIDR_LINESIZE_MASK) + 4); + + /* If FEAT_CCIDX is enabled, CCSIDR_EL1 has a different bit layout */ + if ( (id_aa64mmfr2_el1 >> ID_AA64MMFR2_CCIDX_SHIFT) & 0x7 ) + { + ccsidr_numsets_shift = CCSIDR_NUMSETS_SHIFT_FEAT_CCIDX; + ccsidr_numsets_mask = CCSIDR_NUMSETS_MASK_FEAT_CCIDX; + } + + /* Arm ARM: (Number of sets in cache) - 1 */ + num_sets = ((ccsidr_el1 >> ccsidr_numsets_shift) & ccsidr_numsets_mask) + 1; + + printk(XENLOG_INFO "LLC found: L%u (line size: %u bytes, sets num: %u)\n", + n, line_size, num_sets); + + /* Restore value in CSSELR_EL1 */ + WRITE_SYSREG(csselr_el1, CSSELR_EL1); + isb(); + + return line_size * num_sets; +} + +void __init arch_llc_coloring_init(void) {} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 424744ad5e..c72c90302e 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -746,6 +747,8 @@ void asmlinkage __init start_xen(unsigned long boot_phys_offset, printk("Command line: %s\n", cmdline); cmdline_parse(cmdline); + llc_coloring_init(); + setup_mm(); vm_init(); diff --git a/xen/common/llc-coloring.c b/xen/common/llc-coloring.c index db96a83ddd..51eae90ad5 100644 --- a/xen/common/llc-coloring.c +++ b/xen/common/llc-coloring.c @@ -8,7 +8,7 @@ #include #include -static bool __ro_after_init llc_coloring_enabled; +bool __ro_after_init llc_coloring_enabled; boolean_param("llc-coloring", llc_coloring_enabled); static unsigned int __initdata llc_size; diff --git a/xen/include/xen/llc-coloring.h b/xen/include/xen/llc-coloring.h index c60c8050c5..67b27c995b 100644 --- a/xen/include/xen/llc-coloring.h +++ b/xen/include/xen/llc-coloring.h @@ -11,10 +11,14 @@ #include #ifdef CONFIG_LLC_COLORING +extern bool llc_coloring_enabled; + void llc_coloring_init(void); void dump_llc_coloring_info(void); void domain_dump_llc_colors(const struct domain *d); #else +#define llc_coloring_enabled false + static inline void llc_coloring_init(void) {} static inline void dump_llc_coloring_info(void) {} static inline void domain_dump_llc_colors(const struct domain *d) {}