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pr=C From: Stewart Hildebrand To: CC: Volodymyr Babchuk , Stewart Hildebrand , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v14 5/5] arm/vpci: honor access size when returning an error Date: Tue, 14 May 2024 10:33:57 -0400 Message-ID: <20240514143400.152280-6-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240514143400.152280-1-stewart.hildebrand@amd.com> References: <20240514143400.152280-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CC:EE_|SN7PR12MB7977:EE_ X-MS-Office365-Filtering-Correlation-Id: b0ef63ab-8853-4624-2182-08dc742312ce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|376005|1800799015|82310400017; X-Microsoft-Antispam-Message-Info: IRQdCSQ76CNm6BAyrpNWu5W0Gq18D7L2QRGuVj/HmSj/CzJC4jYK+lHewJNV3Hs8qrW5bw2bfysC+foYio+wSwdyR00iSU04q6j1+Hc1sX2X2jzUytJHyJLxgW7dVIyP+bag4ZBUBxMVcADEAiSs3RrPnsvZEIq0JP+UV+suf/LGZkzoIkPfS6QxOk6ALoB3eH5Jk8pUuvMy3e90hT4exui8/iBSeTT3C4kWPsTyx48NmNB04VxOKrbK/vb7pGeSr2c+yIsJoZt3PqpOd0qBx+Z5rXYCFfN154T5XKRxKTnMnYMJYcttO46TS8zBqB9BqKmITd/NEhYVToRZYNkLXLLqDu2p7dcSowzFI0mbkoP94USOU592ipnRLywEbvmygRezWq1amjayu1yNRk7nK+0u5WkmwWJG3p6m4T3H8DOfcT2o9yzCbaKLsY5NR5ENRrON+R6qo4Bti31bcoGNUp2rv8mkAYqHuA6IL3svTEDmxcfQEsZPLupFPm5oYNLDGKITcb3y83v3eE2iGzoFNaBRMC4cRP6w1zSE9xoRwuBNDd4/v5oK2O99EUOM/BnqhjnU70FfmA1xozo3//Q36umcghy+x9sXELvjX3gOW6EPmQBtxto4KNbxdhy+tU26BykBsqnVNm/b6ZqV7cqwGfgrgyFPPMYNNlIFNaP+CpSyiQ4PqQAszP7MZKieC8bDjAury1gtLU2JX5EzwH4TCQZ2Bbs4JBKHugGN+pI5oFQMUwlACJwWvIAf0qdots9GEDqDh0Q0bgCX7J2AFiYG+MQ/zqZNgN6grXY2UCJ37dNOCzV6pK+5073+POfBs6UPF1/ffgUw1yp2S1c0PM+ZoQDmDoiSbjnv3+haJ1ma/RKNajqRpXv/Lw+rd0zJ+KRn0IJPqPc1/9slHeDj4EDH6OeK7o/5B/XicthcsON4g0KbEwWgp7cWdeeCa+xrnk8POs2hjyBVU8SpGKapdIsunQoJLEWK91c0AAecqSTsqzlEBzb2522+2mpzkcNv9iRqV3dKhGYW+SFEIMxBHkRZHuJV4m9bKoeR3NzXDMaIxb4q+YtcuwVfFTEwRjDhNqkYOKw0z8z7DlVwxPAy40KLieAIEckLM8FR3n96PMQDPnBaBe5TRDzfXx4N3VCl11FFtcBtaLfIOPzopF/ecGeND0sZCbJB1xo822faNOgTOM18SyJNZbM4Wz/lKvo34oZ7Kgu25AxVjo8ulytX55hmVFDWm3NuEkJGP43afHgZUjgYjVP8iZ+sB00YHinpFPBPv4HXaFcfLjPWxIAi0uoPKYLvFovlxYQca7sJVDqBxSMWNrPddZ9hirmZ4Q6OQPD5w+l9vkeBob5sYaftr9nE7pcn6/fNIaERq3hM3sDw4nMLJBL+As1P2HEZIJkWBt7U X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(36860700004)(376005)(1800799015)(82310400017);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 May 2024 14:35:16.6850 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b0ef63ab-8853-4624-2182-08dc742312ce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7977 From: Volodymyr Babchuk Guest can try to read config space using different access sizes: 8, 16, 32, 64 bits. We need to take this into account when we are returning an error back to MMIO handler, otherwise it is possible to provide more data than requested: i.e. guest issues LDRB instruction to read one byte, but we are writing 0xFFFFFFFFFFFFFFFF in the target register. Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand Acked-by: Julien Grall --- v9->10: * New patch in v10. --- xen/arch/arm/vpci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vpci.c b/xen/arch/arm/vpci.c index 348ba0fbc860..aaf9d9120c3d 100644 --- a/xen/arch/arm/vpci.c +++ b/xen/arch/arm/vpci.c @@ -41,6 +41,8 @@ static int vpci_mmio_read(struct vcpu *v, mmio_info_t *info, { struct pci_host_bridge *bridge = p; pci_sbdf_t sbdf; + const uint8_t access_size = (1 << info->dabt.size) * 8; + const uint64_t access_mask = GENMASK_ULL(access_size - 1, 0); /* data is needed to prevent a pointer cast on 32bit */ unsigned long data; @@ -48,7 +50,7 @@ static int vpci_mmio_read(struct vcpu *v, mmio_info_t *info, if ( !vpci_sbdf_from_gpa(v->domain, bridge, info->gpa, &sbdf) ) { - *r = ~0UL; + *r = access_mask; return 1; } @@ -59,7 +61,7 @@ static int vpci_mmio_read(struct vcpu *v, mmio_info_t *info, return 1; } - *r = ~0UL; + *r = access_mask; return 0; }