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Smith" , Stewart Hildebrand , Jiqian Chen , Huang Rui Subject: [XEN PATCH v12 3/7] x86/pvh: Add PHYSDEVOP_setup_gsi for PVH dom0 Date: Mon, 8 Jul 2024 19:41:20 +0800 Message-ID: <20240708114124.407797-4-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240708114124.407797-1-Jiqian.Chen@amd.com> References: <20240708114124.407797-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00005FFC:EE_|MW4PR12MB7432:EE_ X-MS-Office365-Filtering-Correlation-Id: 7091c7f4-b1fa-430b-79d2-08dc9f42f75d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013|7416014; X-Microsoft-Antispam-Message-Info: SPucu6IMkVwJuyqLy+kkNrIm8wEv+5Q2BvhGUlMZxTH5Ndq7AnPbBI3UWVfprAD/Iq4yJplyn9CNL5kg8haVFdl7WitxItdsiOXAxgWLx+Em8dYXLr18haYfTf4fi8MM7/Y5ZkU4CoMwe1bQyqhmHl47cD9wkDsx8tTixh8c0cB622scGoaB4fCgvoJwseNXTAoKRGkX6LPJ0pYlZ1TmE60NQxhwfAY5CAxXtt9oF0NY2VZrdpTtqbuTjvodz8cQa2Xp2TUrMjM69z8AMusALKoi8hqbsEQHwj7R1WVeWPxQnebrwlz1uvZsRfin254Z8zfZ0nvOERoRvNN0ecS9LLic0c3jvQTLdLEhbWs0TWP+UWK1aMv6x9Vh2Uyfg7877GMI+48Yqt7CrJO6YNpwjQ9C+W9vRMhumxeJ5mn3J9Ox2QKDVaN3De0eJx5Qex6064/w1blCo2m0tvsbr+aDkMeImKli4baJRgu2I1qzihwER+/86WT3u54meFIklSqmaehkQQT3EgzpEc6IIT5V0ksw5Q5BvnNO7MN1UL/ntafEK52KnGtbDj09yNPfADgBJwkh0jmbUqs5hQCbtkp6jKRQ3ZAAPdKMIOLTW90oYLLDVqFffBZL2ZDGFEeGxpYVsvHz9LUtXyrVrEXrsKijUv9PQL/43suhsSrY15Ogvu3T2bMaXWOMSlhpiYzczGCBJkbRHmUaqwEPr3Q74Nu2hiErg0NvkXpZ24nxvidls4kf4IoPH8v1u+BA4KwLnPpx7xQ0QaET2XE7BOSwFzeE/FAPe3poPs6lmqoFWkeceQbDi77wzazxCHuUYaPr9GOqCEpuQPLlJtYuorOPBL50N4C9N/OsX+Ryoe1PQkw3bIX/NYGi9oS18TniK2jAi+jmy9rLufTDyd6U7l5H6ZG+1YoqkGNmGOSlmYI/FVl5NThEA/0/EZlryh0kzWx5cFR3wlYAA+3DBcZcutt5F3++mSSD1uIXkosmlxteUW3lm8JUw8fUnE+kIRazIsG3EsEChfGf4pSFz/2fAj87VIciUN7B1L1AQV7Nz34j9gbv8IOBmVeyN4HYgPsvSIMF5fGtwPUNK2A+u4Yumutoa7PxQNKTkRGhi/3avf1oG/8qYfpZLj/pCPdumIL4MDCJSK2yKJk+Mqhz2if+E3Pv7MJUh7UpnWPP1IWt0+XMaoVPFQZBxJekwc/wsJL0M06bsy2YmluFs/wbePAYslRMqWmNo0oaurlFzvxNDR0x0dWXmbAMiVaWEOltGr2dNmc102ZtvRXAWCBHddQZElVzbIdI9Eu+3F78yJji9A7F8+6RskfIKb2qqnznaIc+ZsJNOj4v67z70Il30h5IaeGp0aVpT0+MZyI4xNx6RhqIf9qYX8x04o0K/tUNfhDD+9bXppCas0BbOXK8Pt3/hhJ4gju5rTUeSXioh9jZnc/Lg3THufc+tixPT8FnQaGvzw0BqdP+ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2024 11:41:54.5742 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7091c7f4-b1fa-430b-79d2-08dc9f42f75d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00005FFC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7432 The gsi of a passthrough device must be configured for it to be able to be mapped into a hvm domU. But When dom0 is PVH, the gsis may not get registered(see below clarification), it causes the info of apic, pin and irq not be added into irq_2_pin list, and the handler of irq_desc is not set, then when passthrough a device, setting ioapic affinity and vector will fail. To fix above problem, on Linux kernel side, a new code will need to call PHYSDEVOP_setup_gsi for passthrough devices to register gsi when dom0 is PVH. So, add PHYSDEVOP_setup_gsi into hvm_physdev_op for above purpose. Clarify two questions: First, why the gsi of devices belong to PVH dom0 can work? Because when probe a driver to a normal device, it uses the normal probe function of pci device, in its callstack, it requests irq and unmask corresponding ioapic of gsi, then trap into xen and register gsi finally. Callstack is(on linux kernel side) pci_device_probe-> request_threaded_irq-> irq_startup-> __unmask_ioapic-> io_apic_write, then trap into xen hvmemul_do_io-> hvm_io_intercept-> hvm_process_io_intercept-> vioapic_write_indirect-> vioapic_hwdom_map_gsi-> mp_register_gsi. So that the gsi can be registered. Second, why the gsi of passthrough device can't work when dom0 is PVH? Because when assign a device to passthrough, it uses the specific probe function of pciback, in its callstack, it doesn't install a fake irq handler due to the ISR is not running. So that mp_register_gsi on Xen side is never called, then the gsi is not registered. Callstack is(on linux kernel side) pcistub_probe->pcistub_seize-> pcistub_init_device-> xen_pcibk_reset_device-> xen_pcibk_control_isr->isr_on==0. Signed-off-by: Jiqian Chen Signed-off-by: Huang Rui Signed-off-by: Jiqian Chen Reviewed-by: Stefano Stabellini --- xen/arch/x86/hvm/hypercall.c | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/x86/hvm/hypercall.c b/xen/arch/x86/hvm/hypercall.c index 03ada3c880bd..cfe82d0f96ed 100644 --- a/xen/arch/x86/hvm/hypercall.c +++ b/xen/arch/x86/hvm/hypercall.c @@ -86,6 +86,7 @@ long hvm_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg) return -ENOSYS; break; + case PHYSDEVOP_setup_gsi: case PHYSDEVOP_pci_mmcfg_reserved: case PHYSDEVOP_pci_device_add: case PHYSDEVOP_pci_device_remove: