@@ -231,6 +231,16 @@ config TBOOT
If unsure, stay with the default.
+config X86_PSR
+ bool "Platform Shared Resource support" if EXPERT
+ default INTEL
+ help
+ Support of Platform Shared Resource technology, which is basis for
+ monitoring and control of resources like cache and memory bandwidth.
+ See xl-psr documentation for details.
+
+ If unsure, stay with the default.
+
choice
prompt "Alignment of Xen image"
default XEN_ALIGN_2M if PV_SHIM_EXCLUSIVE
@@ -57,7 +57,7 @@ obj-y += pci.o
obj-y += percpu.o
obj-y += physdev.o
obj-$(CONFIG_COMPAT) += x86_64/physdev.o
-obj-y += psr.o
+obj-$(CONFIG_X86_PSR) += psr.o
obj-y += setup.o
obj-y += shutdown.o
obj-y += smp.o
@@ -1195,6 +1195,7 @@ long arch_do_domctl(
case XEN_DOMCTL_psr_alloc:
switch ( domctl->u.psr_alloc.cmd )
{
+#ifdef CONFIG_X86_PSR
case XEN_DOMCTL_PSR_SET_L3_CBM:
ret = psr_set_val(d, domctl->u.psr_alloc.target,
domctl->u.psr_alloc.data,
@@ -1257,6 +1258,8 @@ long arch_do_domctl(
#undef domctl_psr_get_val
+#endif /* CONFIG_X86_PSR */
+
default:
ret = -EOPNOTSUPP;
break;
@@ -69,12 +69,11 @@ extern struct psr_cmt *psr_cmt;
static inline bool psr_cmt_enabled(void)
{
- return !!psr_cmt;
+ return IS_ENABLED(CONFIG_X86_PSR) && psr_cmt;
}
int psr_alloc_rmid(struct domain *d);
void psr_free_rmid(struct domain *d);
-void psr_ctxt_switch_to(struct domain *d);
int psr_get_info(unsigned int socket, enum psr_type type,
uint32_t data[], unsigned int array_len);
@@ -83,8 +82,15 @@ int psr_get_val(struct domain *d, unsigned int socket,
int psr_set_val(struct domain *d, unsigned int socket,
uint64_t new_val, enum psr_type type);
+#ifdef CONFIG_X86_PSR
+void psr_ctxt_switch_to(struct domain *d);
void psr_domain_init(struct domain *d);
void psr_domain_free(struct domain *d);
+#else
+static inline void psr_ctxt_switch_to(struct domain *d) {}
+static inline void psr_domain_init(struct domain *d) {}
+static inline void psr_domain_free(struct domain *d) {}
+#endif
#endif /* __ASM_PSR_H__ */
@@ -225,10 +225,11 @@ long arch_do_sysctl(
case XEN_SYSCTL_psr_alloc:
{
- uint32_t data[PSR_INFO_ARRAY_SIZE] = { };
+ uint32_t __maybe_unused data[PSR_INFO_ARRAY_SIZE] = { };
switch ( sysctl->u.psr_alloc.cmd )
{
+#ifdef CONFIG_X86_PSR
case XEN_SYSCTL_PSR_get_l3_info:
ret = psr_get_info(sysctl->u.psr_alloc.target,
PSR_TYPE_L3_CBM, data, ARRAY_SIZE(data));
@@ -279,6 +280,7 @@ long arch_do_sysctl(
if ( __copy_field_to_guest(u_sysctl, sysctl, u.psr_alloc) )
ret = -EFAULT;
break;
+#endif /* CONFIG_X86_PSR */
default:
ret = -EOPNOTSUPP;
Xen's implementation of PSR only supports Intel CPUs right now, hence it can be made dependant on CONFIG_INTEL build option. Since platform implementation is not limited to single vendor, intermediate option CONFIG_X86_PSR introduced, which selected by CONFIG_INTEL. When !X86_PSR then PSR-related sysctls XEN_SYSCTL_psr_cmt_op & XEN_SYSCTL_psr_alloc are off as well. Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com> CC: Jan Beulich <jbeulich@suse.com> CC: Andrew Cooper <andrew.cooper3@citrix.com> --- v5 patch here: https://lore.kernel.org/xen-devel/20240918091517.1200080-1-Sergiy_Kibrik@epam.com/ changes in v6: - rename option PSR -> X86_PSR - add help text for X86_PSR option and default value - do not force X86_PSR option by 'select' changes in v5: - simplify psr_cmt_enabled() - move PSR config option and add description changes in v4: - introduced CONFIG_PSR - changed description - changes to psr stubs --- xen/arch/x86/Kconfig | 10 ++++++++++ xen/arch/x86/Makefile | 2 +- xen/arch/x86/domctl.c | 3 +++ xen/arch/x86/include/asm/psr.h | 10 ++++++++-- xen/arch/x86/sysctl.c | 4 +++- 5 files changed, 25 insertions(+), 4 deletions(-)