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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2024 12:13:24.5387 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9b904da-e4f7-4005-4c43-08dd07ca66d2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003447.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7587 After the regions have been created, now we enable the MPU. For this we disable the background region so that the new memory map created for the regions take effect. Also, we treat all RW regions as non executable and the data cache is enabled. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Acked-by: Julien Grall --- Changes from :- v2 - 1. Extracted from the previous patch into a new one. 2. Disabled background region. v3 - 1. Removed dsb before setting SCTLR_EL2. The reason being From ARM DDI 0487K.a D23-7349: "Direct writes to these registers (includes SCTLR_EL2) are not allowed to affect any instructions appearing in program order before the direct write." So, we don't need a synchronization barrier before writing to SCTLR_EL2. Further, we do have synchronization barriers after writing the MPU region registers (which happens before we read SCTLR_EL2). So, SCTLR_EL2 is written after the MPU registers are synchronized. And, thus adding a 'isb' to flush the instruction pipeline ensures that the subsequent instructions are fetched after the MPU has been enabled. 2. Saved and restored lr in enable_boot_cpu_mm(). v4 - 1. Moved the definition of SCTLR_ELx_BR from sysregs.h from head.S. The reason being sysregs.h does not exist any longer (refer to previous patch for details) and SCTLR_ELx_BR is used in head.S only. (I have preserved the R-b abd A-b, let me know if that is ok). v5 - 1. No changes. xen/arch/arm/arm64/mpu/head.S | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index 1ab65e8ebb..c56c693cc2 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -5,6 +5,9 @@ #include +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + #define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ #define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ #define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ @@ -73,6 +76,29 @@ FUNC_LOCAL(fail_insufficient_regions) b 1b END(fail_insufficient_regions) +/* + * Enable EL2 MPU and data cache + * If the Background region is enabled, then the MPU uses the default memory + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch64 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region here. + * + * Clobbers x0 + * + */ +FUNC_LOCAL(enable_mpu) + mrs x0, SCTLR_EL2 + bic x0, x0, #SCTLR_ELx_BR /* Disable Background region */ + orr x0, x0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr x0, x0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + orr x0, x0, #SCTLR_Axx_ELx_WXN /* Enable WXN */ + msr SCTLR_EL2, x0 + isb + + ret +END(enable_mpu) + /* * Maps the various sections of Xen (described in xen.lds.S) as different MPU * regions. @@ -112,6 +138,7 @@ FUNC(enable_boot_cpu_mm) ldr x2, =__bss_end prepare_xen_region x0, x1, x2, x3, x4, x5 + b enable_mpu ret END(enable_boot_cpu_mm)