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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v4 1/3] xen/arm: Move some of the functions to common file Date: Thu, 3 Apr 2025 18:12:39 +0100 Message-ID: <20250403171241.975377-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250403171241.975377-1-ayan.kumar.halder@amd.com> References: <20250403171241.975377-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD6:EE_|IA1PR12MB6356:EE_ X-MS-Office365-Filtering-Correlation-Id: bbc10902-0735-4d6b-f89f-08dd72d2c811 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: MzbSPx4qmyJBklvTR8GMBHK+kCEYa7SHo1gQKBogzY9wMZbbIdJH8gnhdM6ttZYRj0SdP0qwt1u0gTf0rpgVcsKspF56/8XwSNbRwJPoMBp+5eOqMZrtTxgyBIGQQMJXTnErM+WMdtOrqWnbd7JP5knp123Gk1/ISRqJBhrmlAMqcI/hJnhF1f+i6wmYBBM94MzjBnlJUVJRPKA++q/4ATKqS8woU0d0/ecgjKV/iFKZmPkNq8+sW/8P5ywi+HLqHVowvNOHUdmZcZ9dIWms70VigqiDxfCaadD+QS5aEw3s2JFBqCo0exjWrWnPHc91J8AaG6G3GjK+AM4aMeJGJuauKESlMkXCzkYq+kF5iHpfMK+3TT0hD63QyBUcnwfxx6ycBKdQZjNvqHdTOiNgjXEWwLF2TVYJMqcdyUt52ZovD0wr7cSThH1kijEbkYX0LC5CcC7ADxPeAtO/MLWbrWTWwDM8n8rBURPhtxq2BTUR72vuFdQEGlkpKmRfBymrMC0Kc5nLaC2ZbowPojWxhIOiEszR74JCjsp+qGZDUFNXol6PefcyAr1C94DfsDM0tRmgSJklos5xGKheUqyWrF2JcTHeCHA7TQusHJJ9kNlcKnsMyygCmUVBFeDmbzDjd5hzGIPAW6gKsYGzkGkdTnPqnlSu+nhwyx8cKNMNM3P397tyIDBSM9LJy9wmPsbZFa0BdxwY+MWhNTMSXa7AdPD48/DGIaqbI0zwQ9doNA+mh56jLcOjO3ndzzYYCTfEiwRVT2t/LbqAeVujlTzNIzTA6y7wnO2D0L0c1SNznzYtoorV8A8WUYlRaY88XpPgdg4dvQw8iSgs3fhagNtU/N0vHRBMlJj8nBsO7/8DgA92nU3J4YEj9o4lsdaqrHGOIBWp+BXUN6pVpGFEfcXyl0I0mwFucWwu8GWQY7wXXa6Ue8fvQW/8pS2MgI6B7ctnUxGSQpyjy1YpXQ88KtVbCKgeQgrHM2F2U/9kgQky/5c2+UDqIN/M3GgwciuwiT2NgwFqHnx/dGYpeCm7FlVzp2dSg0+oAwTkZ64nW4ByhoyTfF+5glm9kUW9hDVCSutlz1RuLwaSxUFJV3Nd6Qh05YEhsoiy8/3tQhVguR+rQaEh2p+f8NGdFeaCHyGe2ea3OQmoCWS/CuuUD3fn5bFDa5XmusSMamA8Ol3Tksh9uNwNEfKzk8/bfilBlC57T9sO9hqmxM+4t2mofxFTAbWG6V3mzii+7OEddToOopkHaLZABDH2zCPd4mAWOCkp/qGMMCpz3O+c8tx5i9DQsx+E9XOcFzjCVWccPg4xm9ihzCY8alAQPDLfJ9n+Oh9U1XOmCKwOAnq5bcLTcy6DrqzXmHH04LdBsdeJcqEdqnJATAn846f4XEXsnlRWNLjmB75hazoM5xw2QT2VcswTahdlnrRj40SM1/rh2AWnrY2VVKDbsNHiMc1FMjMW34BlS62oN8hqd0M0DAQGm5thPpD2Qln2fx5o/Fut2ax0fY43sog= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2025 17:12:58.0235 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bbc10902-0735-4d6b-f89f-08dd72d2c811 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6356 Added a new file prepare_xen_region.inc to hold the common earlyboot MPU regions configurations across arm64 and arm32. prepare_xen_region, fail_insufficient_regions() will be used by both arm32 and arm64. Thus, they have been moved to prepare_xen_region.inc. enable_secondary_cpu_mm() is a stub which is moved to prepare_xen_region.inc as SMP is currently not supported for MPU. *_PRBAR are moved to arm64/sysregs.h. *_PRLAR are moved to prepare_xen_region.inc as they are common between arm32 and arm64. Introduce WRITE_SYSREG_ASM to write to the system registers from the common asm file. Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Extracted the arm64 head.S functions/macros in a common file. v3 - 1. Moved *_PRLAR are moved to prepare_xen_region.inc 2. enable_boot_cpu_mm() is preserved in mpu/head.S. 3. STORE_SYSREG is renamed as WRITE_SYSREG_ASM() 4. LOAD_SYSREG is removed. 5. No need to save/restore lr in enable_boot_cpu_mm(). IOW, keep it as it was in the original code. xen/arch/arm/arm64/mpu/head.S | 88 +----------------- xen/arch/arm/include/asm/arm64/sysregs.h | 11 +++ .../include/asm/mpu/prepare_xen_region.inc | 89 +++++++++++++++++++ 3 files changed, 101 insertions(+), 87 deletions(-) create mode 100644 xen/arch/arm/include/asm/mpu/prepare_xen_region.inc diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index ed01993d85..8cd8107a13 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -3,83 +3,7 @@ * Start-of-day code for an Armv8-R MPU system. */ -#include -#include - -/* Backgroud region enable/disable */ -#define SCTLR_ELx_BR BIT(17, UL) - -#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ -#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ -#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ -#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */ - -#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ -#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ - -/* - * Macro to prepare and set a EL2 MPU memory region. - * We will also create an according MPU memory region entry, which - * is a structure of pr_t, in table \prmap. - * - * sel: region selector - * base: reg storing base address - * limit: reg storing limit address - * prbar: store computed PRBAR_EL2 value - * prlar: store computed PRLAR_EL2 value - * maxcount: maximum number of EL2 regions supported - * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be - * REGION_DATA_PRBAR - * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be - * REGION_NORMAL_PRLAR - * - * Preserves \maxcount - * Output: - * \sel: Next available region selector index. - * Clobbers \base, \limit, \prbar, \prlar - * - * Note that all parameters using registers should be distinct. - */ -.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR - /* Check if the region is empty */ - cmp \base, \limit - beq 1f - - /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ - cmp \sel, \maxcount - bge fail_insufficient_regions - - /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ - and \base, \base, #MPU_REGION_MASK - mov \prbar, #\attr_prbar - orr \prbar, \prbar, \base - - /* Limit address should be inclusive */ - sub \limit, \limit, #1 - and \limit, \limit, #MPU_REGION_MASK - mov \prlar, #\attr_prlar - orr \prlar, \prlar, \limit - - msr PRSELR_EL2, \sel - isb - msr PRBAR_EL2, \prbar - msr PRLAR_EL2, \prlar - dsb sy - isb - - add \sel, \sel, #1 - -1: -.endm - -/* - * Failure caused due to insufficient MPU regions. - */ -FUNC_LOCAL(fail_insufficient_regions) - PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") -1: wfe - b 1b -END(fail_insufficient_regions) +#include /* * Enable EL2 MPU and data cache @@ -154,16 +78,6 @@ FUNC(enable_boot_cpu_mm) ret END(enable_boot_cpu_mm) -/* - * We don't yet support secondary CPUs bring-up. Implement a dummy helper to - * please the common code. - */ -FUNC(enable_secondary_cpu_mm) - PRINT("- SMP not enabled yet -\r\n") -1: wfe - b 1b -END(enable_secondary_cpu_mm) - /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h index b593e4028b..3ee3715430 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,15 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff +#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ +#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ +#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */ + +#define WRITE_SYSREG_ASM(v, name) "msr " __stringify(name,) #v; + +#ifndef __ASSEMBLY__ + /* Access to system registers */ #define WRITE_SYSREG64(v, name) do { \ @@ -481,6 +490,8 @@ #define WRITE_SYSREG_LR(v, index) WRITE_SYSREG(v, ICH_LR_REG(index)) #define READ_SYSREG_LR(index) READ_SYSREG(ICH_LR_REG(index)) +#endif /* __ASSEMBLY__ */ + #endif /* _ASM_ARM_ARM64_SYSREGS_H */ /* diff --git a/xen/arch/arm/include/asm/mpu/prepare_xen_region.inc b/xen/arch/arm/include/asm/mpu/prepare_xen_region.inc new file mode 100644 index 0000000000..8af44d5669 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/prepare_xen_region.inc @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + +#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * sel: region selector + * base: reg storing base address + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be + * REGION_NORMAL_PRLAR + * + * Preserves maxcount + * Output: + * sel: Next available region selector index. + * Clobbers base, limit, prbar, prlar + * + * Note that all parameters using registers should be distinct. + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR + /* Check if the region is empty */ + cmp \base, \limit + beq 1f + + /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ + cmp \sel, \maxcount + bge fail_insufficient_regions + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + WRITE_SYSREG_ASM(\sel, PRSELR_EL2) + isb + WRITE_SYSREG_ASM(\prbar, PRBAR_EL2) + WRITE_SYSREG_ASM(\prlar, PRLAR_EL2) + dsb sy + isb + + add \sel, \sel, #1 + +1: +.endm + +/* Failure caused due to insufficient MPU regions. */ +FUNC_LOCAL(fail_insufficient_regions) + PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") +1: wfe + b 1b +END(fail_insufficient_regions) + +/* + * We don't yet support secondary CPUs bring-up. Implement a dummy helper to + * please the common code. + */ +FUNC(enable_secondary_cpu_mm) + PRINT("- SMP not enabled yet -\r\n") +1: wfe + b 1b +END(enable_secondary_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */