| Message ID | 2141998496.8765382.1592320789155.JavaMail.zimbra@cert.pl (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Implement support for external IPT monitoring | expand |
On 16.06.2020 17:19, Michał Leszczyński wrote: > --- a/xen/include/asm-x86/msr-index.h > +++ b/xen/include/asm-x86/msr-index.h > @@ -621,4 +621,41 @@ > #define MSR_PKGC9_IRTL 0x00000634 > #define MSR_PKGC10_IRTL 0x00000635 > > +/* Intel PT MSRs */ > +#define MSR_IA32_RTIT_CTL 0x00000570 > +#define RTIT_CTL_TRACEEN (1ULL << 0) > +#define RTIT_CTL_CYCEN (1ULL << 1) > +#define RTIT_CTL_OS (1ULL << 2) > +#define RTIT_CTL_USR (1ULL << 3) > +#define RTIT_CTL_PWR_EVT_EN (1ULL << 4) > +#define RTIT_CTL_FUP_ON_PTW (1ULL << 5) > +#define RTIT_CTL_FABRIC_EN (1ULL << 6) > +#define RTIT_CTL_CR3_FILTER (1ULL << 7) > +#define RTIT_CTL_TOPA (1ULL << 8) > +#define RTIT_CTL_MTC_EN (1ULL << 9) > +#define RTIT_CTL_TSC_EN (1ULL << 10) > +#define RTIT_CTL_DIS_RETC (1ULL << 11) > +#define RTIT_CTL_PTW_EN (1ULL << 12) > +#define RTIT_CTL_BRANCH_EN (1ULL << 13) > +#define RTIT_CTL_MTC_FREQ_OFFSET 14 > +#define RTIT_CTL_MTC_FREQ (0x0fULL << RTIT_CTL_MTC_FREQ_OFFSET) > +#define RTIT_CTL_CYC_THRESH_OFFSET 19 > +#define RTIT_CTL_CYC_THRESH (0x0fULL << RTIT_CTL_CYC_THRESH_OFFSET) > +#define RTIT_CTL_PSB_FREQ_OFFSET 24 > +#define RTIT_CTL_PSB_FREQ (0x0fULL << RTIT_CTL_PSB_FREQ_OFFSET) > +#define RTIT_CTL_ADDR_OFFSET(n) (32 + 4 * (n)) > +#define RTIT_CTL_ADDR(n) (0x0fULL << RTIT_CTL_ADDR_OFFSET(n)) > +#define MSR_IA32_RTIT_STATUS 0x00000571 > +#define RTIT_STATUS_FILTER_EN (1ULL << 0) > +#define RTIT_STATUS_CONTEXT_EN (1ULL << 1) > +#define RTIT_STATUS_TRIGGER_EN (1ULL << 2) > +#define RTIT_STATUS_ERROR (1ULL << 4) > +#define RTIT_STATUS_STOPPED (1ULL << 5) > +#define RTIT_STATUS_BYTECNT (0x1ffffULL << 32) > +#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 > +#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 > +#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 > +#define MSR_IA32_RTIT_ADDR_A(n) (0x00000580 + (n) * 2) > +#define MSR_IA32_RTIT_ADDR_B(n) (0x00000581 + (n) * 2) Please honor the comment at the top of the file as well as the one separating new content from not necessarily well-formed one further down. I also think Andrew wants no IA32 infixes anymore in new additions, albeit I'm still not fully convinced the resulting deviation from SDM naming is really helpful. Jan
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index b328a47ed8..ecf0dd8bab 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -621,4 +621,41 @@ #define MSR_PKGC9_IRTL 0x00000634 #define MSR_PKGC10_IRTL 0x00000635 +/* Intel PT MSRs */ +#define MSR_IA32_RTIT_CTL 0x00000570 +#define RTIT_CTL_TRACEEN (1ULL << 0) +#define RTIT_CTL_CYCEN (1ULL << 1) +#define RTIT_CTL_OS (1ULL << 2) +#define RTIT_CTL_USR (1ULL << 3) +#define RTIT_CTL_PWR_EVT_EN (1ULL << 4) +#define RTIT_CTL_FUP_ON_PTW (1ULL << 5) +#define RTIT_CTL_FABRIC_EN (1ULL << 6) +#define RTIT_CTL_CR3_FILTER (1ULL << 7) +#define RTIT_CTL_TOPA (1ULL << 8) +#define RTIT_CTL_MTC_EN (1ULL << 9) +#define RTIT_CTL_TSC_EN (1ULL << 10) +#define RTIT_CTL_DIS_RETC (1ULL << 11) +#define RTIT_CTL_PTW_EN (1ULL << 12) +#define RTIT_CTL_BRANCH_EN (1ULL << 13) +#define RTIT_CTL_MTC_FREQ_OFFSET 14 +#define RTIT_CTL_MTC_FREQ (0x0fULL << RTIT_CTL_MTC_FREQ_OFFSET) +#define RTIT_CTL_CYC_THRESH_OFFSET 19 +#define RTIT_CTL_CYC_THRESH (0x0fULL << RTIT_CTL_CYC_THRESH_OFFSET) +#define RTIT_CTL_PSB_FREQ_OFFSET 24 +#define RTIT_CTL_PSB_FREQ (0x0fULL << RTIT_CTL_PSB_FREQ_OFFSET) +#define RTIT_CTL_ADDR_OFFSET(n) (32 + 4 * (n)) +#define RTIT_CTL_ADDR(n) (0x0fULL << RTIT_CTL_ADDR_OFFSET(n)) +#define MSR_IA32_RTIT_STATUS 0x00000571 +#define RTIT_STATUS_FILTER_EN (1ULL << 0) +#define RTIT_STATUS_CONTEXT_EN (1ULL << 1) +#define RTIT_STATUS_TRIGGER_EN (1ULL << 2) +#define RTIT_STATUS_ERROR (1ULL << 4) +#define RTIT_STATUS_STOPPED (1ULL << 5) +#define RTIT_STATUS_BYTECNT (0x1ffffULL << 32) +#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 +#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 +#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 +#define MSR_IA32_RTIT_ADDR_A(n) (0x00000580 + (n) * 2) +#define MSR_IA32_RTIT_ADDR_B(n) (0x00000581 + (n) * 2) + #endif /* __ASM_MSR_INDEX_H */
Define constants related to Intel Processor Trace features. Signed-off-by: Michal Leszczynski <michal.leszczynski@cert.pl> --- xen/include/asm-x86/msr-index.h | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+)