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t=1654486858; x= 1654573258; bh=Ul/YTZELjdXhM4yte1+Tqag6FgjJfdtEGmy0W8pthfU=; b=H suzKn2Dd738Q1vwBxYukEroFNsufQJddh/iizV9eAY9HQy3+DB+EXVF4HtfcLq5+ ds0kHEwJ/ou3x7dzPw0xH4hRSu/SI0I4jQlZXUtfhauoiiXNCVmKdiYFjiqo6suM bRwnPkVPdlo/cozd7u8zB9nCx/zNeVt4DtIZ7RMMhY5uilfqut0svYg4i02abqw2 MoESh5Xluc9vOouB/Y9eZQKR5+nc9KjV0Tfh0KUr3olyFQSlylgY/LrUxyd0IW4V mORk2Zbs+ohdDYmxemPQIcLnseOX8JYHEwQcTQM1pNx9rdTvIvW7DLjC2RVc17bs KS4dmqvwSta545M1uRDmQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedruddtuddgjeefucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpeforghr vghkucforghrtgiihihkohifshhkihdqifpkrhgvtghkihcuoehmrghrmhgrrhgvkhesih hnvhhishhisghlvghthhhinhhgshhlrggsrdgtohhmqeenucggtffrrghtthgvrhhnpefg ueduhefgvdefheehudejheefudevueeghfekhfehleegveduteeuiedugffgffenucevlh hushhtvghrufhiiigvpedvnecurfgrrhgrmhepmhgrihhlfhhrohhmpehmrghrmhgrrhgv khesihhnvhhishhisghlvghthhhinhhgshhlrggsrdgtohhm X-ME-Proxy: Feedback-ID: i1568416f:Fastmail From: =?utf-8?q?Marek_Marczykowski-G=C3=B3recki?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?q?Marek_Marczykowski-G=C3=B3recki?= , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [RFC PATCH 12/12] xue: allow driving the reset of XHCI by a domain while Xen uses DbC Date: Mon, 6 Jun 2022 05:40:24 +0200 Message-Id: <2f7660330861b1c6db9520332bee20388178c162.1654486751.git-series.marmarek@invisiblethingslab.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 That's possible, because the capability was designed specifically to allow separate driver handle it, in parallel to unmodified xhci driver (separate set of registers, pretending the port is "disconnected" for the main xhci driver etc). It works with Linux dom0, although requires an awful hack - re-enabling bus mastering behind dom0's backs. Linux driver does similar thing - see drivers/usb/early/xhci-dbc.c:xdbc_handle_events(). To avoid Linux messing with the DbC, mark this MMIO area as read-only. Signed-off-by: Marek Marczykowski-Górecki --- xen/drivers/char/xue.c | 13 +++++++------ xen/include/xue.h | 10 ++++++++++ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/xen/drivers/char/xue.c b/xen/drivers/char/xue.c index ff62b868e906..437ed6468630 100644 --- a/xen/drivers/char/xue.c +++ b/xen/drivers/char/xue.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #define XUE_POLL_INTERVAL 100 /* us */ @@ -71,12 +72,12 @@ static void __init cf_check xue_uart_init_postirq(struct serial_port *port) init_timer(&uart->timer, xue_uart_poll, port, 0); set_timer(&uart->timer, NOW() + MILLISECS(1)); - if ( pci_ro_device(0, (uart->xue.xhc_cf8 >> 16) & 0xff, - (uart->xue.xhc_cf8 >> 8) & 0xff) ) - printk(XENLOG_INFO "Could not mark config space of %02x:%02x.%u read-only.\n", - (uart->xue.xhc_cf8 >> 16) & 0xff, - (uart->xue.xhc_cf8 >> 11) & 0x1f, - (uart->xue.xhc_cf8 >> 8) & 0x0f); +#ifdef CONFIG_X86 + if ( rangeset_add_range(mmio_ro_ranges, + PFN_DOWN(uart->xue.xhc_mmio_phys + uart->xue.xhc_dbc_offset), + PFN_UP(uart->xue.xhc_mmio_phys + uart->xue.xhc_dbc_offset + sizeof(*uart->xue.dbc_reg)) - 1) ) + printk(XENLOG_INFO "Error while adding MMIO range of device to mmio_ro_ranges\n"); +#endif } static int cf_check xue_uart_tx_ready(struct serial_port *port) diff --git a/xen/include/xue.h b/xen/include/xue.h index b1f304958679..87b821429fd8 100644 --- a/xen/include/xue.h +++ b/xen/include/xue.h @@ -1818,6 +1818,7 @@ static inline void xue_flush(struct xue *xue, struct xue_trb_ring *trb, { struct xue_dbc_reg *reg = xue->dbc_reg; uint32_t db = (reg->db & 0xFFFF00FF) | (trb->db << 8); + uint32_t cmd; if (xue->open && !(reg->ctrl & (1UL << XUE_CTRL_DCE))) { if (!xue_init_dbc(xue)) { @@ -1829,6 +1830,15 @@ static inline void xue_flush(struct xue *xue, struct xue_trb_ring *trb, xue_enable_dbc(xue); } + /* Re-enable bus mastering, if dom0 (or other) disabled it in the meantime. */ + cmd = xue_pci_read(xue, xue->xhc_cf8, 1); +#define XUE_XHCI_CMD_REQUIRED (PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER) + if ((cmd & XUE_XHCI_CMD_REQUIRED) != XUE_XHCI_CMD_REQUIRED) { + cmd |= XUE_XHCI_CMD_REQUIRED; + xue_pci_write(xue, xue->xhc_cf8, 1, cmd); + } +#undef XUE_XHCI_CMD_REQUIRED + xue_pop_events(xue); if (!(reg->ctrl & (1UL << XUE_CTRL_DCR))) {