| Message ID | 3617dc882193166580ae7e5d122447e924cab524.1674226563.git.oleksii.kurochko@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISCV basic exception handling implementation | expand |
On 20/01/2023 2:59 pm, Oleksii Kurochko wrote: > Work with some registers requires csr command which is part of > Zicsr. > > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> > --- > xen/arch/riscv/arch.mk | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk > index 012dc677c3..95b41d9f3e 100644 > --- a/xen/arch/riscv/arch.mk > +++ b/xen/arch/riscv/arch.mk > @@ -10,7 +10,7 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > # into the upper half _or_ the lower half of the address space. > # -mcmodel=medlow would force Xen into the lower half. > > -CFLAGS += -march=$(riscv-march-y) -mstrict-align -mcmodel=medany > +CFLAGS += -march=$(riscv-march-y)_zicsr -mstrict-align -mcmodel=medany Should we just go straight for G, rather than bumping it along every time we make a tweak? ~Andrew
On Fri, 2023-01-20 at 15:29 +0000, Andrew Cooper wrote: > On 20/01/2023 2:59 pm, Oleksii Kurochko wrote: > > Work with some registers requires csr command which is part of > > Zicsr. > > > > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> > > --- > > xen/arch/riscv/arch.mk | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk > > index 012dc677c3..95b41d9f3e 100644 > > --- a/xen/arch/riscv/arch.mk > > +++ b/xen/arch/riscv/arch.mk > > @@ -10,7 +10,7 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := > > $(riscv-march-y)c > > # into the upper half _or_ the lower half of the address space. > > # -mcmodel=medlow would force Xen into the lower half. > > > > -CFLAGS += -march=$(riscv-march-y) -mstrict-align -mcmodel=medany > > +CFLAGS += -march=$(riscv-march-y)_zicsr -mstrict-align - > > mcmodel=medany > > Should we just go straight for G, rather than bumping it along every > time we make a tweak? > I didn't go straight for G as it represents the “IMAFDZicsr Zifencei” base and extensions thereby it will be needed to add support for FPU (at least it requires {save,restore}_fp_state) but I am not sure that we need it in general. Another one reason is that Linux kernel introduces _zicsr extenstion separately (but I am not sure that it can be considered as a serious argument): https://elixir.bootlin.com/linux/latest/source/arch/riscv/Makefile#L58 https://lore.kernel.org/all/20221024113000.891820486@linuxfoundation.org/ > ~Andrew ~Oleksii
On Mon, Jan 23, 2023 at 8:43 PM Oleksii <oleksii.kurochko@gmail.com> wrote: > > On Fri, 2023-01-20 at 15:29 +0000, Andrew Cooper wrote: > > On 20/01/2023 2:59 pm, Oleksii Kurochko wrote: > > > Work with some registers requires csr command which is part of > > > Zicsr. > > > > > > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> > > > --- > > > xen/arch/riscv/arch.mk | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk > > > index 012dc677c3..95b41d9f3e 100644 > > > --- a/xen/arch/riscv/arch.mk > > > +++ b/xen/arch/riscv/arch.mk > > > @@ -10,7 +10,7 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := > > > $(riscv-march-y)c > > > # into the upper half _or_ the lower half of the address space. > > > # -mcmodel=medlow would force Xen into the lower half. > > > > > > -CFLAGS += -march=$(riscv-march-y) -mstrict-align -mcmodel=medany > > > +CFLAGS += -march=$(riscv-march-y)_zicsr -mstrict-align - > > > mcmodel=medany > > > > Should we just go straight for G, rather than bumping it along every > > time we make a tweak? > > > I didn't go straight for G as it represents the “IMAFDZicsr Zifencei” > base and extensions thereby it will be needed to add support for FPU > (at least it requires {save,restore}_fp_state) but I am not sure that > we need it in general. That seems fair enough. I don't see a reason to restrict ourselves if we aren't using something. Although we probably will hit a requirement on G at some point anyway. Alistair > > Another one reason is that Linux kernel introduces _zicsr extenstion > separately (but I am not sure that it can be considered as a serious > argument): > https://elixir.bootlin.com/linux/latest/source/arch/riscv/Makefile#L58 > https://lore.kernel.org/all/20221024113000.891820486@linuxfoundation.org/ > > > ~Andrew > ~Oleksii > >
On Tue, 2023-01-31 at 21:49 +1000, Alistair Francis wrote: > On Mon, Jan 23, 2023 at 8:43 PM Oleksii <oleksii.kurochko@gmail.com> > wrote: > > > > On Fri, 2023-01-20 at 15:29 +0000, Andrew Cooper wrote: > > > On 20/01/2023 2:59 pm, Oleksii Kurochko wrote: > > > > Work with some registers requires csr command which is part of > > > > Zicsr. > > > > > > > > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> > > > > --- > > > > xen/arch/riscv/arch.mk | 2 +- > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk > > > > index 012dc677c3..95b41d9f3e 100644 > > > > --- a/xen/arch/riscv/arch.mk > > > > +++ b/xen/arch/riscv/arch.mk > > > > @@ -10,7 +10,7 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := > > > > $(riscv-march-y)c > > > > # into the upper half _or_ the lower half of the address > > > > space. > > > > # -mcmodel=medlow would force Xen into the lower half. > > > > > > > > -CFLAGS += -march=$(riscv-march-y) -mstrict-align - > > > > mcmodel=medany > > > > +CFLAGS += -march=$(riscv-march-y)_zicsr -mstrict-align - > > > > mcmodel=medany > > > > > > Should we just go straight for G, rather than bumping it along > > > every > > > time we make a tweak? > > > > > I didn't go straight for G as it represents the “IMAFDZicsr > > Zifencei” > > base and extensions thereby it will be needed to add support for > > FPU > > (at least it requires {save,restore}_fp_state) but I am not sure > > that > > we need it in general. > > That seems fair enough. I don't see a reason to restrict ourselves if > we aren't using something. Although we probably will hit a > requirement > on G at some point anyway. > Thanks for your notes so I will change it to G. > Alistair > > > > > Another one reason is that Linux kernel introduces _zicsr > > extenstion > > separately (but I am not sure that it can be considered as a > > serious > > argument): > > https://elixir.bootlin.com/linux/latest/source/arch/riscv/Makefile#L58 > > https://lore.kernel.org/all/20221024113000.891820486@linuxfoundation.org/ > > > > > ~Andrew > > ~Oleksii > > > >
diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index 012dc677c3..95b41d9f3e 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -10,7 +10,7 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c # into the upper half _or_ the lower half of the address space. # -mcmodel=medlow would force Xen into the lower half. -CFLAGS += -march=$(riscv-march-y) -mstrict-align -mcmodel=medany +CFLAGS += -march=$(riscv-march-y)_zicsr -mstrict-align -mcmodel=medany # TODO: Drop override when more of the build is working override ALL_OBJS-y = arch/$(TARGET_ARCH)/built_in.o
Work with some registers requires csr command which is part of Zicsr. Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> --- xen/arch/riscv/arch.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)