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Ip=[91.120.43.17]; Helo=[owabud.epam.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR03MB0812 Cc: Julien Grall , Stefano Stabellini Subject: [Xen-devel] [PATCH] xen/arm: Fix macro for ARM Jazelle CPU feature identification X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Fix macro for ARM Jazelle CPU feature identification: value of 0 indicates that CPU does not support ARM Jazelle (PFR0[11:8]) Coverity-ID: 1381849 Signed-off-by: Artem Mygaiev Reviewed-by: Julien Grall --- xen/include/asm-arm/cpufeature.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index af60fe3..c0a25ae 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -24,7 +24,7 @@ #define cpu_has_arm (boot_cpu_feature32(arm) == 1) #define cpu_has_thumb (boot_cpu_feature32(thumb) >= 1) #define cpu_has_thumb2 (boot_cpu_feature32(thumb) >= 3) -#define cpu_has_jazelle (boot_cpu_feature32(jazelle) >= 0) +#define cpu_has_jazelle (boot_cpu_feature32(jazelle) > 0) #define cpu_has_thumbee (boot_cpu_feature32(thumbee) == 1) #define cpu_has_aarch32 (cpu_has_arm || cpu_has_thumb)