| Message ID | 460c58c78e956ca62cc80356536dbdb45fa73779.1743756934.git.teddy.astie@vates.tech (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2,1/2] x86/amd: Add guest support for AMD TCE | expand |
On 04/04/2025 10:49 am, Teddy Astie wrote: > diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c > index d70abb7e0c..0e2e7d012f 100644 > --- a/xen/arch/x86/setup.c > +++ b/xen/arch/x86/setup.c > @@ -2008,6 +2008,14 @@ void asmlinkage __init noreturn __start_xen(void) > if ( cpu_has_pku ) > set_in_cr4(X86_CR4_PKE); > > + if ( cpu_has_tce ) > + { > + printk("Enabling AMD TCE\n"); > + > + write_efer(read_efer() | EFER_TCE); > + trampoline_efer |= EFER_TCE; This doesn't do what you think it does. (it writes into the copy of the trampoline in .init, not the one placed in low memory). You need to use bootsym() to get to the real trampoline. I'm also not sure the prinkt() is useful. It's about universal on AMD systems. ~Andrew
diff --git a/CHANGELOG.md b/CHANGELOG.md index dbfecefbd4..375905e68a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -18,7 +18,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) - Support PCI passthrough for HVM domUs when dom0 is PVH (note SR-IOV capability usage is not yet supported on PVH dom0). - Smoke tests for the FreeBSD Xen builds in Cirrus CI. - - Guest support for AMD Translation Cache Extension feature. + - Guest and Xen support for AMD Translation Cache Extension feature. ### Removed diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index 05399fb9c9..ab6d07b767 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -114,6 +114,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_xop boot_cpu_has(X86_FEATURE_XOP) #define cpu_has_skinit boot_cpu_has(X86_FEATURE_SKINIT) #define cpu_has_fma4 boot_cpu_has(X86_FEATURE_FMA4) +#define cpu_has_tce boot_cpu_has(X86_FEATURE_TCE) #define cpu_has_tbm boot_cpu_has(X86_FEATURE_TBM) /* CPUID level 0x0000000D:1.eax */ diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index d70abb7e0c..0e2e7d012f 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -2008,6 +2008,14 @@ void asmlinkage __init noreturn __start_xen(void) if ( cpu_has_pku ) set_in_cr4(X86_CR4_PKE); + if ( cpu_has_tce ) + { + printk("Enabling AMD TCE\n"); + + write_efer(read_efer() | EFER_TCE); + trampoline_efer |= EFER_TCE; + } + if ( opt_invpcid && cpu_has_invpcid ) use_invpcid = true;
Aside exposing this flag to guests, Xen can also make use of it to reduce the cost of some TLB flushes. Enable this flag if supported by hardware. Signed-off-by: Teddy Astie <teddy.astie@vates.tech> --- v2: - Add changelog entry - use trampoline_efer - use cpu_has_tce instead of opencoded boot_cpu_has(X86_FEATURE_TCE) --- CHANGELOG.md | 2 +- xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/setup.c | 8 ++++++++ 3 files changed, 10 insertions(+), 1 deletion(-)