From patchwork Wed Feb 10 12:57:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 8271581 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D697EBEEED for ; Wed, 10 Feb 2016 13:00:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BBC112037F for ; Wed, 10 Feb 2016 13:00:31 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 542FC20381 for ; Wed, 10 Feb 2016 13:00:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aTULJ-0006q9-GX; Wed, 10 Feb 2016 12:58:01 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aTULH-0006pu-Mp for xen-devel@lists.xenproject.org; Wed, 10 Feb 2016 12:57:59 +0000 Received: from [193.109.254.147] by server-5.bemta-14.messagelabs.com id 62/B6-23366-7D33BB65; Wed, 10 Feb 2016 12:57:59 +0000 X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-13.tower-27.messagelabs.com!1455109076!22802791!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 30601 invoked from network); 10 Feb 2016 12:57:57 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-13.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 10 Feb 2016 12:57:57 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Wed, 10 Feb 2016 05:57:56 -0700 Message-Id: <56BB41E002000078000D08B1@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Wed, 10 Feb 2016 05:57:52 -0700 From: "Jan Beulich" To: "xen-devel" References: <56BB3DE902000078000D087A@prv-mh.provo.novell.com> In-Reply-To: <56BB3DE902000078000D087A@prv-mh.provo.novell.com> Mime-Version: 1.0 Cc: Andrew Cooper , Keir Fraser Subject: [Xen-devel] [PATCH 3/3] x86: rename X86_FEATURE_{CLFLSH -> CLFLUSH} X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is both more natural and in line with a Linux change (between 3.14 and 3.15). Signed-off-by: Jan Beulich x86: rename X86_FEATURE_{CLFLSH -> CLFLUSH} This is both more natural and in line with a Linux change (between 3.14 and 3.15). Signed-off-by: Jan Beulich --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -206,7 +206,7 @@ static void __init early_cpu_detect(void c->x86_mask = eax & 15; edx &= ~cleared_caps[cpufeat_word(X86_FEATURE_FPU)]; ecx &= ~cleared_caps[cpufeat_word(X86_FEATURE_XMM3)]; - if (edx & cpufeat_mask(X86_FEATURE_CLFLSH)) + if (edx & cpufeat_mask(X86_FEATURE_CLFLUSH)) c->x86_cache_alignment = ((ebx >> 8) & 0xff) * 8; /* Leaf 0x1 capabilities filled in early for Xen. */ c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = edx; @@ -251,7 +251,7 @@ static void generic_identify(struct cpui c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = edx; c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] = ecx; - if ( cpu_has(c, X86_FEATURE_CLFLSH) ) + if ( cpu_has(c, X86_FEATURE_CLFLUSH) ) c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8; if ( (c->cpuid_level >= CPUID_PM_LEAF) && --- a/xen/include/asm-x86/amd.h +++ b/xen/include/asm-x86/amd.h @@ -11,17 +11,17 @@ /* Family 0Fh, Revision C */ #define AMD_FEATURES_K8_REV_C_ECX 0 -#define AMD_FEATURES_K8_REV_C_EDX ( \ - cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) | \ - cpufeat_mask(X86_FEATURE_DE) | cpufeat_mask(X86_FEATURE_PSE) | \ - cpufeat_mask(X86_FEATURE_TSC) | cpufeat_mask(X86_FEATURE_MSR) | \ - cpufeat_mask(X86_FEATURE_PAE) | cpufeat_mask(X86_FEATURE_MCE) | \ - cpufeat_mask(X86_FEATURE_CX8) | cpufeat_mask(X86_FEATURE_APIC) | \ - cpufeat_mask(X86_FEATURE_SEP) | cpufeat_mask(X86_FEATURE_MTRR) | \ - cpufeat_mask(X86_FEATURE_PGE) | cpufeat_mask(X86_FEATURE_MCA) | \ - cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) | \ - cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_CLFLSH)| \ - cpufeat_mask(X86_FEATURE_MMX) | cpufeat_mask(X86_FEATURE_FXSR) | \ +#define AMD_FEATURES_K8_REV_C_EDX ( \ + cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) | \ + cpufeat_mask(X86_FEATURE_DE) | cpufeat_mask(X86_FEATURE_PSE) | \ + cpufeat_mask(X86_FEATURE_TSC) | cpufeat_mask(X86_FEATURE_MSR) | \ + cpufeat_mask(X86_FEATURE_PAE) | cpufeat_mask(X86_FEATURE_MCE) | \ + cpufeat_mask(X86_FEATURE_CX8) | cpufeat_mask(X86_FEATURE_APIC) | \ + cpufeat_mask(X86_FEATURE_SEP) | cpufeat_mask(X86_FEATURE_MTRR) | \ + cpufeat_mask(X86_FEATURE_PGE) | cpufeat_mask(X86_FEATURE_MCA) | \ + cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) | \ + cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_CLFLUSH)| \ + cpufeat_mask(X86_FEATURE_MMX) | cpufeat_mask(X86_FEATURE_FXSR) | \ cpufeat_mask(X86_FEATURE_XMM) | cpufeat_mask(X86_FEATURE_XMM2)) #define AMD_EXTFEATURES_K8_REV_C_ECX 0 #define AMD_EXTFEATURES_K8_REV_C_EDX ( \ --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -32,7 +32,7 @@ #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ #define X86_FEATURE_PN (0*32+18) /* Processor serial number */ -#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */ +#define X86_FEATURE_CLFLUSH (0*32+19) /* Supports the CLFLUSH instruction */ #define X86_FEATURE_DS (0*32+21) /* Debug Store */ #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ @@ -197,7 +197,7 @@ #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) #define cpu_has_mp 1 #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) -#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) +#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH) #define cpu_has_page1gb boot_cpu_has(X86_FEATURE_PAGE1GB) #define cpu_has_fsgsbase boot_cpu_has(X86_FEATURE_FSGSBASE) #define cpu_has_aperfmperf boot_cpu_has(X86_FEATURE_APERFMPERF) Reviewed-by: Andrew Cooper --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -206,7 +206,7 @@ static void __init early_cpu_detect(void c->x86_mask = eax & 15; edx &= ~cleared_caps[cpufeat_word(X86_FEATURE_FPU)]; ecx &= ~cleared_caps[cpufeat_word(X86_FEATURE_XMM3)]; - if (edx & cpufeat_mask(X86_FEATURE_CLFLSH)) + if (edx & cpufeat_mask(X86_FEATURE_CLFLUSH)) c->x86_cache_alignment = ((ebx >> 8) & 0xff) * 8; /* Leaf 0x1 capabilities filled in early for Xen. */ c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = edx; @@ -251,7 +251,7 @@ static void generic_identify(struct cpui c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = edx; c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] = ecx; - if ( cpu_has(c, X86_FEATURE_CLFLSH) ) + if ( cpu_has(c, X86_FEATURE_CLFLUSH) ) c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8; if ( (c->cpuid_level >= CPUID_PM_LEAF) && --- a/xen/include/asm-x86/amd.h +++ b/xen/include/asm-x86/amd.h @@ -11,17 +11,17 @@ /* Family 0Fh, Revision C */ #define AMD_FEATURES_K8_REV_C_ECX 0 -#define AMD_FEATURES_K8_REV_C_EDX ( \ - cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) | \ - cpufeat_mask(X86_FEATURE_DE) | cpufeat_mask(X86_FEATURE_PSE) | \ - cpufeat_mask(X86_FEATURE_TSC) | cpufeat_mask(X86_FEATURE_MSR) | \ - cpufeat_mask(X86_FEATURE_PAE) | cpufeat_mask(X86_FEATURE_MCE) | \ - cpufeat_mask(X86_FEATURE_CX8) | cpufeat_mask(X86_FEATURE_APIC) | \ - cpufeat_mask(X86_FEATURE_SEP) | cpufeat_mask(X86_FEATURE_MTRR) | \ - cpufeat_mask(X86_FEATURE_PGE) | cpufeat_mask(X86_FEATURE_MCA) | \ - cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) | \ - cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_CLFLSH)| \ - cpufeat_mask(X86_FEATURE_MMX) | cpufeat_mask(X86_FEATURE_FXSR) | \ +#define AMD_FEATURES_K8_REV_C_EDX ( \ + cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) | \ + cpufeat_mask(X86_FEATURE_DE) | cpufeat_mask(X86_FEATURE_PSE) | \ + cpufeat_mask(X86_FEATURE_TSC) | cpufeat_mask(X86_FEATURE_MSR) | \ + cpufeat_mask(X86_FEATURE_PAE) | cpufeat_mask(X86_FEATURE_MCE) | \ + cpufeat_mask(X86_FEATURE_CX8) | cpufeat_mask(X86_FEATURE_APIC) | \ + cpufeat_mask(X86_FEATURE_SEP) | cpufeat_mask(X86_FEATURE_MTRR) | \ + cpufeat_mask(X86_FEATURE_PGE) | cpufeat_mask(X86_FEATURE_MCA) | \ + cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) | \ + cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_CLFLUSH)| \ + cpufeat_mask(X86_FEATURE_MMX) | cpufeat_mask(X86_FEATURE_FXSR) | \ cpufeat_mask(X86_FEATURE_XMM) | cpufeat_mask(X86_FEATURE_XMM2)) #define AMD_EXTFEATURES_K8_REV_C_ECX 0 #define AMD_EXTFEATURES_K8_REV_C_EDX ( \ --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -32,7 +32,7 @@ #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ #define X86_FEATURE_PN (0*32+18) /* Processor serial number */ -#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */ +#define X86_FEATURE_CLFLUSH (0*32+19) /* Supports the CLFLUSH instruction */ #define X86_FEATURE_DS (0*32+21) /* Debug Store */ #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ @@ -197,7 +197,7 @@ #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) #define cpu_has_mp 1 #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) -#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) +#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH) #define cpu_has_page1gb boot_cpu_has(X86_FEATURE_PAGE1GB) #define cpu_has_fsgsbase boot_cpu_has(X86_FEATURE_FSGSBASE) #define cpu_has_aperfmperf boot_cpu_has(X86_FEATURE_APERFMPERF)