From patchwork Mon Feb 15 12:06:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 8314001 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6FA4E9F6E4 for ; Mon, 15 Feb 2016 12:09:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6E8612039E for ; Mon, 15 Feb 2016 12:09:42 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5E362201FA for ; Mon, 15 Feb 2016 12:09:41 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aVHvO-0000RQ-L6; Mon, 15 Feb 2016 12:06:42 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aVHvM-0000RL-QT for xen-devel@lists.xenproject.org; Mon, 15 Feb 2016 12:06:41 +0000 Received: from [85.158.137.68] by server-9.bemta-3.messagelabs.com id 67/4A-03066-05FB1C65; Mon, 15 Feb 2016 12:06:40 +0000 X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-7.tower-31.messagelabs.com!1455537997!14979278!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 35414 invoked from network); 15 Feb 2016 12:06:38 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-7.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 15 Feb 2016 12:06:38 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Mon, 15 Feb 2016 05:06:37 -0700 Message-Id: <56C1CD5902000078000D2107@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Mon, 15 Feb 2016 05:06:33 -0700 From: "Jan Beulich" To: "xen-devel" Mime-Version: 1.0 Cc: Andrew Cooper , Keir Fraser Subject: [Xen-devel] [PATCH] x86emul: relax asm() constraints X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Let's give the compiler as much liberty in picking instruction operands as possible. Also drop unnecessary size modifiers when the correct size can already be derived from the asm() operands. Finally also drop an "unsigned" from idiv_dbl()'s second parameter, allowing a cast to be eliminated. Signed-off-by: Jan Beulich x86emul: relax asm() constraints Let's give the compiler as much liberty in picking instruction operands as possible. Also drop unnecessary size modifiers when the correct size can already be derived from the asm() operands. Finally also drop an "unsigned" from idiv_dbl()'s second parameter, allowing a cast to be eliminated. Signed-off-by: Jan Beulich --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -611,7 +611,7 @@ do { */ static bool_t even_parity(uint8_t v) { - asm ( "test %b0,%b0; setp %b0" : "=a" (v) : "0" (v) ); + asm ( "test %1,%1; setp %0" : "=qm" (v) : "q" (v) ); return v; } @@ -813,9 +813,9 @@ static int read_ulong( */ static bool_t mul_dbl(unsigned long m[2]) { - bool_t rc = 0; - asm ( "mul %1; seto %b2" - : "+a" (m[0]), "+d" (m[1]), "+q" (rc) ); + bool_t rc; + asm ( "mul %1; seto %2" + : "+a" (m[0]), "+d" (m[1]), "=q" (rc) ); return rc; } @@ -826,9 +826,9 @@ static bool_t mul_dbl(unsigned long m[2] */ static bool_t imul_dbl(unsigned long m[2]) { - bool_t rc = 0; + bool_t rc; asm ( "imul %1; seto %b2" - : "+a" (m[0]), "+d" (m[1]), "+q" (rc) ); + : "+a" (m[0]), "+d" (m[1]), "=q" (rc) ); return rc; } @@ -854,9 +854,9 @@ static bool_t div_dbl(unsigned long u[2] * NB. We don't use idiv directly as it's moderately hard to work out * ahead of time whether it will #DE, which we cannot allow to happen. */ -static bool_t idiv_dbl(unsigned long u[2], unsigned long v) +static bool_t idiv_dbl(unsigned long u[2], long v) { - bool_t negu = (long)u[1] < 0, negv = (long)v < 0; + bool_t negu = (long)u[1] < 0, negv = v < 0; /* u = abs(u) */ if ( negu ) @@ -4542,9 +4542,10 @@ x86_emulate( case 0xbc: /* bsf or tzcnt */ { bool_t zf; - asm ( "bsf %2,%0; setz %b1" + + asm ( "bsf %2,%0; setz %1" : "=r" (dst.val), "=q" (zf) - : "r" (src.val) ); + : "rm" (src.val) ); _regs.eflags &= ~EFLG_ZF; if ( (vex.pfx == vex_f3) && vcpu_has_bmi1() ) { @@ -4567,9 +4568,10 @@ x86_emulate( case 0xbd: /* bsr or lzcnt */ { bool_t zf; - asm ( "bsr %2,%0; setz %b1" + + asm ( "bsr %2,%0; setz %1" : "=r" (dst.val), "=q" (zf) - : "r" (src.val) ); + : "rm" (src.val) ); _regs.eflags &= ~EFLG_ZF; if ( (vex.pfx == vex_f3) && vcpu_has_lzcnt() ) { @@ -4698,7 +4700,7 @@ x86_emulate( break; case 4: #ifdef __x86_64__ - asm ( "bswap %k0" : "=r" (dst.val) : "0" (*dst.reg) ); + asm ( "bswap %k0" : "=r" (dst.val) : "0" (*(uint32_t *)dst.reg) ); break; case 8: #endif --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -611,7 +611,7 @@ do { */ static bool_t even_parity(uint8_t v) { - asm ( "test %b0,%b0; setp %b0" : "=a" (v) : "0" (v) ); + asm ( "test %1,%1; setp %0" : "=qm" (v) : "q" (v) ); return v; } @@ -813,9 +813,9 @@ static int read_ulong( */ static bool_t mul_dbl(unsigned long m[2]) { - bool_t rc = 0; - asm ( "mul %1; seto %b2" - : "+a" (m[0]), "+d" (m[1]), "+q" (rc) ); + bool_t rc; + asm ( "mul %1; seto %2" + : "+a" (m[0]), "+d" (m[1]), "=q" (rc) ); return rc; } @@ -826,9 +826,9 @@ static bool_t mul_dbl(unsigned long m[2] */ static bool_t imul_dbl(unsigned long m[2]) { - bool_t rc = 0; + bool_t rc; asm ( "imul %1; seto %b2" - : "+a" (m[0]), "+d" (m[1]), "+q" (rc) ); + : "+a" (m[0]), "+d" (m[1]), "=q" (rc) ); return rc; } @@ -854,9 +854,9 @@ static bool_t div_dbl(unsigned long u[2] * NB. We don't use idiv directly as it's moderately hard to work out * ahead of time whether it will #DE, which we cannot allow to happen. */ -static bool_t idiv_dbl(unsigned long u[2], unsigned long v) +static bool_t idiv_dbl(unsigned long u[2], long v) { - bool_t negu = (long)u[1] < 0, negv = (long)v < 0; + bool_t negu = (long)u[1] < 0, negv = v < 0; /* u = abs(u) */ if ( negu ) @@ -4542,9 +4542,10 @@ x86_emulate( case 0xbc: /* bsf or tzcnt */ { bool_t zf; - asm ( "bsf %2,%0; setz %b1" + + asm ( "bsf %2,%0; setz %1" : "=r" (dst.val), "=q" (zf) - : "r" (src.val) ); + : "rm" (src.val) ); _regs.eflags &= ~EFLG_ZF; if ( (vex.pfx == vex_f3) && vcpu_has_bmi1() ) { @@ -4567,9 +4568,10 @@ x86_emulate( case 0xbd: /* bsr or lzcnt */ { bool_t zf; - asm ( "bsr %2,%0; setz %b1" + + asm ( "bsr %2,%0; setz %1" : "=r" (dst.val), "=q" (zf) - : "r" (src.val) ); + : "rm" (src.val) ); _regs.eflags &= ~EFLG_ZF; if ( (vex.pfx == vex_f3) && vcpu_has_lzcnt() ) { @@ -4698,7 +4700,7 @@ x86_emulate( break; case 4: #ifdef __x86_64__ - asm ( "bswap %k0" : "=r" (dst.val) : "0" (*dst.reg) ); + asm ( "bswap %k0" : "=r" (dst.val) : "0" (*(uint32_t *)dst.reg) ); break; case 8: #endif