From patchwork Tue Feb 16 10:16:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 8323751 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3703F9F372 for ; Tue, 16 Feb 2016 10:18:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1F52820295 for ; Tue, 16 Feb 2016 10:18:46 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EC4CF20270 for ; Tue, 16 Feb 2016 10:18:44 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aVcfw-0005TE-Bv; Tue, 16 Feb 2016 10:16:08 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aVcfu-0005Sz-F8 for xen-devel@lists.xenproject.org; Tue, 16 Feb 2016 10:16:06 +0000 Received: from [193.109.254.147] by server-12.bemta-14.messagelabs.com id AD/D3-09834-5E6F2C65; Tue, 16 Feb 2016 10:16:05 +0000 X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-11.tower-27.messagelabs.com!1455617762!15554922!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 54784 invoked from network); 16 Feb 2016 10:16:03 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-11.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 16 Feb 2016 10:16:03 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Tue, 16 Feb 2016 03:16:01 -0700 Message-Id: <56C304F002000078000D287D@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Tue, 16 Feb 2016 03:16:00 -0700 From: "Jan Beulich" To: "xen-devel" Mime-Version: 1.0 Cc: Andrew Cooper , Keir Fraser Subject: [Xen-devel] [PATCH v2] x86emul: relax asm() constraints X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Let's give the compiler as much liberty at picking instruction operands as possible. Also drop unnecessary size modifiers when the correct size can already be derived from the asm() operands. Finally also drop an "unsigned" from idiv_dbl()'s second parameter, allowing a cast to be eliminated. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper --- v2: Extend a couple of "=q" to "=qm" and one (in div_dbl()) "r" to "rm". x86emul: relax asm() constraints Let's give the compiler as much liberty at picking instruction operands as possible. Also drop unnecessary size modifiers when the correct size can already be derived from the asm() operands. Finally also drop an "unsigned" from idiv_dbl()'s second parameter, allowing a cast to be eliminated. Signed-off-by: Jan Beulich --- v2: Extend a couple of "=q" to "=qm" and one (in div_dbl()) "r" to "rm". --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -611,7 +611,7 @@ do { */ static bool_t even_parity(uint8_t v) { - asm ( "test %b0,%b0; setp %b0" : "=a" (v) : "0" (v) ); + asm ( "test %1,%1; setp %0" : "=qm" (v) : "q" (v) ); return v; } @@ -813,9 +813,9 @@ static int read_ulong( */ static bool_t mul_dbl(unsigned long m[2]) { - bool_t rc = 0; - asm ( "mul %1; seto %b2" - : "+a" (m[0]), "+d" (m[1]), "+q" (rc) ); + bool_t rc; + asm ( "mul %1; seto %2" + : "+a" (m[0]), "+d" (m[1]), "=qm" (rc) ); return rc; } @@ -826,9 +826,9 @@ static bool_t mul_dbl(unsigned long m[2] */ static bool_t imul_dbl(unsigned long m[2]) { - bool_t rc = 0; - asm ( "imul %1; seto %b2" - : "+a" (m[0]), "+d" (m[1]), "+q" (rc) ); + bool_t rc; + asm ( "imul %1; seto %2" + : "+a" (m[0]), "+d" (m[1]), "=qm" (rc) ); return rc; } @@ -842,7 +842,7 @@ static bool_t div_dbl(unsigned long u[2] { if ( (v == 0) || (u[1] >= v) ) return 1; - asm ( "div %2" : "+a" (u[0]), "+d" (u[1]) : "r" (v) ); + asm ( "divq %2" : "+a" (u[0]), "+d" (u[1]) : "rm" (v) ); return 0; } @@ -854,9 +854,9 @@ static bool_t div_dbl(unsigned long u[2] * NB. We don't use idiv directly as it's moderately hard to work out * ahead of time whether it will #DE, which we cannot allow to happen. */ -static bool_t idiv_dbl(unsigned long u[2], unsigned long v) +static bool_t idiv_dbl(unsigned long u[2], long v) { - bool_t negu = (long)u[1] < 0, negv = (long)v < 0; + bool_t negu = (long)u[1] < 0, negv = v < 0; /* u = abs(u) */ if ( negu ) @@ -4542,9 +4542,10 @@ x86_emulate( case 0xbc: /* bsf or tzcnt */ { bool_t zf; - asm ( "bsf %2,%0; setz %b1" - : "=r" (dst.val), "=q" (zf) - : "r" (src.val) ); + + asm ( "bsf %2,%0; setz %1" + : "=r" (dst.val), "=qm" (zf) + : "rm" (src.val) ); _regs.eflags &= ~EFLG_ZF; if ( (vex.pfx == vex_f3) && vcpu_has_bmi1() ) { @@ -4567,9 +4568,10 @@ x86_emulate( case 0xbd: /* bsr or lzcnt */ { bool_t zf; - asm ( "bsr %2,%0; setz %b1" - : "=r" (dst.val), "=q" (zf) - : "r" (src.val) ); + + asm ( "bsr %2,%0; setz %1" + : "=r" (dst.val), "=qm" (zf) + : "rm" (src.val) ); _regs.eflags &= ~EFLG_ZF; if ( (vex.pfx == vex_f3) && vcpu_has_lzcnt() ) { @@ -4698,7 +4700,7 @@ x86_emulate( break; case 4: #ifdef __x86_64__ - asm ( "bswap %k0" : "=r" (dst.val) : "0" (*dst.reg) ); + asm ( "bswap %k0" : "=r" (dst.val) : "0" (*(uint32_t *)dst.reg) ); break; case 8: #endif --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -611,7 +611,7 @@ do { */ static bool_t even_parity(uint8_t v) { - asm ( "test %b0,%b0; setp %b0" : "=a" (v) : "0" (v) ); + asm ( "test %1,%1; setp %0" : "=qm" (v) : "q" (v) ); return v; } @@ -813,9 +813,9 @@ static int read_ulong( */ static bool_t mul_dbl(unsigned long m[2]) { - bool_t rc = 0; - asm ( "mul %1; seto %b2" - : "+a" (m[0]), "+d" (m[1]), "+q" (rc) ); + bool_t rc; + asm ( "mul %1; seto %2" + : "+a" (m[0]), "+d" (m[1]), "=qm" (rc) ); return rc; } @@ -826,9 +826,9 @@ static bool_t mul_dbl(unsigned long m[2] */ static bool_t imul_dbl(unsigned long m[2]) { - bool_t rc = 0; - asm ( "imul %1; seto %b2" - : "+a" (m[0]), "+d" (m[1]), "+q" (rc) ); + bool_t rc; + asm ( "imul %1; seto %2" + : "+a" (m[0]), "+d" (m[1]), "=qm" (rc) ); return rc; } @@ -842,7 +842,7 @@ static bool_t div_dbl(unsigned long u[2] { if ( (v == 0) || (u[1] >= v) ) return 1; - asm ( "div %2" : "+a" (u[0]), "+d" (u[1]) : "r" (v) ); + asm ( "divq %2" : "+a" (u[0]), "+d" (u[1]) : "rm" (v) ); return 0; } @@ -854,9 +854,9 @@ static bool_t div_dbl(unsigned long u[2] * NB. We don't use idiv directly as it's moderately hard to work out * ahead of time whether it will #DE, which we cannot allow to happen. */ -static bool_t idiv_dbl(unsigned long u[2], unsigned long v) +static bool_t idiv_dbl(unsigned long u[2], long v) { - bool_t negu = (long)u[1] < 0, negv = (long)v < 0; + bool_t negu = (long)u[1] < 0, negv = v < 0; /* u = abs(u) */ if ( negu ) @@ -4542,9 +4542,10 @@ x86_emulate( case 0xbc: /* bsf or tzcnt */ { bool_t zf; - asm ( "bsf %2,%0; setz %b1" - : "=r" (dst.val), "=q" (zf) - : "r" (src.val) ); + + asm ( "bsf %2,%0; setz %1" + : "=r" (dst.val), "=qm" (zf) + : "rm" (src.val) ); _regs.eflags &= ~EFLG_ZF; if ( (vex.pfx == vex_f3) && vcpu_has_bmi1() ) { @@ -4567,9 +4568,10 @@ x86_emulate( case 0xbd: /* bsr or lzcnt */ { bool_t zf; - asm ( "bsr %2,%0; setz %b1" - : "=r" (dst.val), "=q" (zf) - : "r" (src.val) ); + + asm ( "bsr %2,%0; setz %1" + : "=r" (dst.val), "=qm" (zf) + : "rm" (src.val) ); _regs.eflags &= ~EFLG_ZF; if ( (vex.pfx == vex_f3) && vcpu_has_lzcnt() ) { @@ -4698,7 +4700,7 @@ x86_emulate( break; case 4: #ifdef __x86_64__ - asm ( "bswap %k0" : "=r" (dst.val) : "0" (*dst.reg) ); + asm ( "bswap %k0" : "=r" (dst.val) : "0" (*(uint32_t *)dst.reg) ); break; case 8: #endif