From patchwork Wed Feb 17 16:32:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 8340971 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B3EBD9F372 for ; Wed, 17 Feb 2016 16:34:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DBDF220279 for ; Wed, 17 Feb 2016 16:34:52 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F014920117 for ; Wed, 17 Feb 2016 16:34:51 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aW51g-0005It-So; Wed, 17 Feb 2016 16:32:28 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aW51e-0005Ih-W3 for xen-devel@lists.xenproject.org; Wed, 17 Feb 2016 16:32:27 +0000 Received: from [193.109.254.147] by server-8.bemta-14.messagelabs.com id 66/8D-24450-A90A4C65; Wed, 17 Feb 2016 16:32:26 +0000 X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-4.tower-27.messagelabs.com!1455726743!23681453!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 54114 invoked from network); 17 Feb 2016 16:32:25 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-4.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 17 Feb 2016 16:32:25 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Wed, 17 Feb 2016 09:32:23 -0700 Message-Id: <56C4AEA502000078000D348C@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Wed, 17 Feb 2016 09:32:21 -0700 From: "Jan Beulich" To: "xen-devel" References: <56C4AC2802000078000D3473@prv-mh.provo.novell.com> In-Reply-To: <56C4AC2802000078000D3473@prv-mh.provo.novell.com> Mime-Version: 1.0 Cc: Andrew Cooper , Keir Fraser Subject: [Xen-devel] [PATCH 1/5] x86emul: fix rIP handling X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Deal with rIP just like with any other register: Truncate to designated width upon entry, write back the zero-extended 32-bit value when emulating 32-bit code, and leave the upper 48 bits unchanged for 16-bit code. Signed-off-by: Jan Beulich x86emul: fix rIP handling Deal with rIP just like with any other register: Truncate to designated width upon entry, write back the zero-extended 32-bit value when emulating 32-bit code, and leave the upper 48 bits unchanged for 16-bit code. Signed-off-by: Jan Beulich --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -570,7 +570,6 @@ do{ asm volatile ( /* Fetch next part of the instruction being emulated. */ #define insn_fetch_bytes(_size) \ ({ unsigned long _x = 0, _eip = _regs.eip; \ - if ( !mode_64bit() ) _eip = (uint32_t)_eip; /* ignore upper dword */ \ _regs.eip += (_size); /* real hardware doesn't truncate */ \ generate_exception_if((uint8_t)(_regs.eip - \ ctxt->regs->eip) > MAX_INST_LEN, \ @@ -1492,6 +1491,10 @@ x86_emulate( #endif } + /* Truncate rIP to def_ad_bytes (2 or 4) if necessary. */ + if ( def_ad_bytes < sizeof(_regs.eip) ) + _regs.eip &= (1UL << (def_ad_bytes * 8)) - 1; + /* Prefix bytes. */ for ( ; ; ) { @@ -3783,6 +3786,21 @@ x86_emulate( /* Commit shadow register state. */ _regs.eflags &= ~EFLG_RF; + switch ( __builtin_expect(def_ad_bytes, sizeof(_regs.eip)) ) + { + uint16_t ip; + + case 2: + ip = _regs.eip; + _regs.eip = ctxt->regs->eip; + *(uint16_t *)&_regs.eip = ip; + break; +#ifdef __x86_64__ + case 4: + _regs.rip = _regs._eip; + break; +#endif + } *ctxt->regs = _regs; done: Reviewed-by: Andrew Cooper --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -570,7 +570,6 @@ do{ asm volatile ( /* Fetch next part of the instruction being emulated. */ #define insn_fetch_bytes(_size) \ ({ unsigned long _x = 0, _eip = _regs.eip; \ - if ( !mode_64bit() ) _eip = (uint32_t)_eip; /* ignore upper dword */ \ _regs.eip += (_size); /* real hardware doesn't truncate */ \ generate_exception_if((uint8_t)(_regs.eip - \ ctxt->regs->eip) > MAX_INST_LEN, \ @@ -1492,6 +1491,10 @@ x86_emulate( #endif } + /* Truncate rIP to def_ad_bytes (2 or 4) if necessary. */ + if ( def_ad_bytes < sizeof(_regs.eip) ) + _regs.eip &= (1UL << (def_ad_bytes * 8)) - 1; + /* Prefix bytes. */ for ( ; ; ) { @@ -3783,6 +3786,21 @@ x86_emulate( /* Commit shadow register state. */ _regs.eflags &= ~EFLG_RF; + switch ( __builtin_expect(def_ad_bytes, sizeof(_regs.eip)) ) + { + uint16_t ip; + + case 2: + ip = _regs.eip; + _regs.eip = ctxt->regs->eip; + *(uint16_t *)&_regs.eip = ip; + break; +#ifdef __x86_64__ + case 4: + _regs.rip = _regs._eip; + break; +#endif + } *ctxt->regs = _regs; done: