From patchwork Tue Feb 23 11:28:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 8391021 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 35E7FC0553 for ; Tue, 23 Feb 2016 11:30:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2ED0E20270 for ; Tue, 23 Feb 2016 11:30:49 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D88A20303 for ; Tue, 23 Feb 2016 11:30:48 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aYB8j-0002Ng-Iq; Tue, 23 Feb 2016 11:28:25 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aYB8i-0002NN-Fh for xen-devel@lists.xenproject.org; Tue, 23 Feb 2016 11:28:24 +0000 Received: from [85.158.137.68] by server-4.bemta-3.messagelabs.com id 76/5F-03606-7524CC65; Tue, 23 Feb 2016 11:28:23 +0000 X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-9.tower-31.messagelabs.com!1456226900!2073895!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 43541 invoked from network); 23 Feb 2016 11:28:22 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-9.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 23 Feb 2016 11:28:22 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Tue, 23 Feb 2016 04:28:20 -0700 Message-Id: <56CC506202000078000D52AD@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Tue, 23 Feb 2016 04:28:18 -0700 From: "Jan Beulich" To: "xen-devel" References: <56CC4F0B02000078000D5290@prv-mh.provo.novell.com> In-Reply-To: <56CC4F0B02000078000D5290@prv-mh.provo.novell.com> Mime-Version: 1.0 Cc: Ian Campbell , Keir Fraser , Ian Jackson , Tim Deegan Subject: [Xen-devel] [PATCH 1/4] ns16550: store pointer to config parameters for PCI X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Subsequent changes will want to use this pointer. This makes the enable_ro structure member redundant, so it gets dropped at once. Signed-off-by: Jan Beulich ns16550: store pointer to config parameters for PCI Subsequent changes will want to use this pointer. This makes the enable_ro structure member redundant, so it gets dropped at once. Signed-off-by: Jan Beulich --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -74,7 +74,7 @@ static struct ns16550 { u32 bar64; u16 cr; u8 bar_idx; - bool_t enable_ro; /* Make MMIO devices read only to Dom0 */ + const struct ns16550_config_param *param; /* Points into .init.*! */ #endif } ns16550_com[2] = { { 0 } }; @@ -624,7 +624,7 @@ static void __init ns16550_init_postirq( #ifdef CONFIG_HAS_PCI if ( uart->bar || uart->ps_bdf_enable ) { - if ( !uart->enable_ro ) + if ( !uart->param ) pci_hide_device(uart->ps_bdf[0], PCI_DEVFN(uart->ps_bdf[1], uart->ps_bdf[2])); else @@ -900,7 +900,7 @@ pci_uart_config(struct ns16550 *uart, bo /* Check for params in uart_config lookup table */ for ( i = 0; i < ARRAY_SIZE(uart_config); i++) { - unsigned int p; + const struct ns16550_config_param *param; if ( uart_config[i].vendor_id != vendor ) continue; @@ -908,33 +908,34 @@ pci_uart_config(struct ns16550 *uart, bo if ( uart_config[i].dev_id != device ) continue; - p = uart_config[i].param; + param = uart_param + uart_config[i].param; + /* * Force length of mmio region to be at least * 8 bytes times (1 << reg_shift) */ - if ( size < (0x8 * (1 << uart_param[p].reg_shift)) ) + if ( size < (0x8 * (1 << param->reg_shift)) ) continue; - if ( bar_idx >= uart_param[p].max_bars ) + if ( bar_idx >= param->max_bars ) continue; - if ( uart_param[p].fifo_size ) - uart->fifo_size = uart_param[p].fifo_size; + uart->param = param; + + if ( param->fifo_size ) + uart->fifo_size = param->fifo_size; - uart->reg_shift = uart_param[p].reg_shift; - uart->reg_width = uart_param[p].reg_width; - uart->lsr_mask = uart_param[p].lsr_mask; + uart->reg_shift = param->reg_shift; + uart->reg_width = param->reg_width; + uart->lsr_mask = param->lsr_mask; uart->io_base = ((u64)bar_64 << 32) | (bar & PCI_BASE_ADDRESS_MEM_MASK); - uart->io_base += uart_param[p].first_offset; - uart->io_base += bar_idx * uart_param[p].uart_offset; - if ( uart_param[p].base_baud ) - uart->clock_hz = uart_param[p].base_baud * 16; - size = max(8U << uart_param[p].reg_shift, - uart_param[p].uart_offset); - /* Set device and MMIO region read only to Dom0 */ - uart->enable_ro = 1; + uart->io_base += param->first_offset; + uart->io_base += bar_idx * param->uart_offset; + if ( param->base_baud ) + uart->clock_hz = param->base_baud * 16; + size = max(8U << param->reg_shift, + param->uart_offset); break; } @@ -1094,10 +1095,6 @@ static void ns16550_init_common(struct n { uart->clock_hz = UART_CLOCK_HZ; -#ifdef CONFIG_HAS_PCI - uart->enable_ro = 0; -#endif - /* Default is no transmit FIFO. */ uart->fifo_size = 1; Reviewed-by: Konrad Rzeszutek Wilk --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -74,7 +74,7 @@ static struct ns16550 { u32 bar64; u16 cr; u8 bar_idx; - bool_t enable_ro; /* Make MMIO devices read only to Dom0 */ + const struct ns16550_config_param *param; /* Points into .init.*! */ #endif } ns16550_com[2] = { { 0 } }; @@ -624,7 +624,7 @@ static void __init ns16550_init_postirq( #ifdef CONFIG_HAS_PCI if ( uart->bar || uart->ps_bdf_enable ) { - if ( !uart->enable_ro ) + if ( !uart->param ) pci_hide_device(uart->ps_bdf[0], PCI_DEVFN(uart->ps_bdf[1], uart->ps_bdf[2])); else @@ -900,7 +900,7 @@ pci_uart_config(struct ns16550 *uart, bo /* Check for params in uart_config lookup table */ for ( i = 0; i < ARRAY_SIZE(uart_config); i++) { - unsigned int p; + const struct ns16550_config_param *param; if ( uart_config[i].vendor_id != vendor ) continue; @@ -908,33 +908,34 @@ pci_uart_config(struct ns16550 *uart, bo if ( uart_config[i].dev_id != device ) continue; - p = uart_config[i].param; + param = uart_param + uart_config[i].param; + /* * Force length of mmio region to be at least * 8 bytes times (1 << reg_shift) */ - if ( size < (0x8 * (1 << uart_param[p].reg_shift)) ) + if ( size < (0x8 * (1 << param->reg_shift)) ) continue; - if ( bar_idx >= uart_param[p].max_bars ) + if ( bar_idx >= param->max_bars ) continue; - if ( uart_param[p].fifo_size ) - uart->fifo_size = uart_param[p].fifo_size; + uart->param = param; + + if ( param->fifo_size ) + uart->fifo_size = param->fifo_size; - uart->reg_shift = uart_param[p].reg_shift; - uart->reg_width = uart_param[p].reg_width; - uart->lsr_mask = uart_param[p].lsr_mask; + uart->reg_shift = param->reg_shift; + uart->reg_width = param->reg_width; + uart->lsr_mask = param->lsr_mask; uart->io_base = ((u64)bar_64 << 32) | (bar & PCI_BASE_ADDRESS_MEM_MASK); - uart->io_base += uart_param[p].first_offset; - uart->io_base += bar_idx * uart_param[p].uart_offset; - if ( uart_param[p].base_baud ) - uart->clock_hz = uart_param[p].base_baud * 16; - size = max(8U << uart_param[p].reg_shift, - uart_param[p].uart_offset); - /* Set device and MMIO region read only to Dom0 */ - uart->enable_ro = 1; + uart->io_base += param->first_offset; + uart->io_base += bar_idx * param->uart_offset; + if ( param->base_baud ) + uart->clock_hz = param->base_baud * 16; + size = max(8U << param->reg_shift, + param->uart_offset); break; } @@ -1094,10 +1095,6 @@ static void ns16550_init_common(struct n { uart->clock_hz = UART_CLOCK_HZ; -#ifdef CONFIG_HAS_PCI - uart->enable_ro = 0; -#endif - /* Default is no transmit FIFO. */ uart->fifo_size = 1;