From patchwork Fri Mar 11 17:33:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 8568181 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C1A209F1C0 for ; Fri, 11 Mar 2016 17:36:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9E0EA20259 for ; Fri, 11 Mar 2016 17:36:14 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 71BF820253 for ; Fri, 11 Mar 2016 17:36:13 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1aeQwe-0004AD-Nu; Fri, 11 Mar 2016 17:33:48 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1aeQwd-0004A4-Lt for xen-devel@lists.xenproject.org; Fri, 11 Mar 2016 17:33:47 +0000 Received: from [85.158.137.68] by server-2.bemta-3.messagelabs.com id 73/AB-03293-A7103E65; Fri, 11 Mar 2016 17:33:46 +0000 X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-13.tower-31.messagelabs.com!1457717623!27988821!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 8.11; banners=-,-,- X-VirusChecked: Checked Received: (qmail 32920 invoked from network); 11 Mar 2016 17:33:45 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-13.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 11 Mar 2016 17:33:45 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Fri, 11 Mar 2016 10:33:43 -0700 Message-Id: <56E30F8802000078000DBB8B@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Fri, 11 Mar 2016 10:33:44 -0700 From: "Jan Beulich" To: "xen-devel" References: <56E30EA102000078000DBB7F@prv-mh.provo.novell.com> In-Reply-To: <56E30EA102000078000DBB7F@prv-mh.provo.novell.com> Mime-Version: 1.0 Cc: Andrew Cooper , Keir Fraser Subject: [Xen-devel] [PATCH 1/3] x86: rename XMM* features to SSE* X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The latter are their canonical names, used already in the instruction emulator. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper x86: rename XMM* features to SSE* The latter are their canonical names, used already in the instruction emulator. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -205,12 +205,12 @@ static void __init early_cpu_detect(void c->x86_model += ((eax >> 16) & 0xF) << 4; c->x86_mask = eax & 15; edx &= ~cleared_caps[cpufeat_word(X86_FEATURE_FPU)]; - ecx &= ~cleared_caps[cpufeat_word(X86_FEATURE_XMM3)]; + ecx &= ~cleared_caps[cpufeat_word(X86_FEATURE_SSE3)]; if (edx & cpufeat_mask(X86_FEATURE_CLFLUSH)) c->x86_cache_alignment = ((ebx >> 8) & 0xff) * 8; /* Leaf 0x1 capabilities filled in early for Xen. */ c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = edx; - c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] = ecx; + c->x86_capability[cpufeat_word(X86_FEATURE_SSE3)] = ecx; if ( cpuid_eax(0x80000000) >= 0x80000008 ) paddr_bits = cpuid_eax(0x80000008) & 0xff; @@ -249,7 +249,7 @@ static void generic_identify(struct cpui c->cpuid_level = cpuid_eax(0); cpuid(0x00000001, &eax, &ebx, &ecx, &edx); c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = edx; - c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] = ecx; + c->x86_capability[cpufeat_word(X86_FEATURE_SSE3)] = ecx; if ( cpu_has(c, X86_FEATURE_CLFLUSH) ) c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8; --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -2029,7 +2029,7 @@ unsigned long hvm_cr4_guest_reserved_bit X86_CR4_PCE | (leaf1_edx & cpufeat_mask(X86_FEATURE_FXSR) ? X86_CR4_OSFXSR : 0) | - (leaf1_edx & cpufeat_mask(X86_FEATURE_XMM) ? + (leaf1_edx & cpufeat_mask(X86_FEATURE_SSE) ? X86_CR4_OSXMMEXCPT : 0) | ((restore || nestedhvm_enabled(v->domain)) && (leaf1_ecx & cpufeat_mask(X86_FEATURE_VMXE)) ? --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1963,7 +1963,7 @@ int nvmx_msr_read_intercept(unsigned int data |= X86_CR4_PGE; if ( edx & cpufeat_mask(X86_FEATURE_FXSR) ) data |= X86_CR4_OSFXSR; - if ( edx & cpufeat_mask(X86_FEATURE_XMM) ) + if ( edx & cpufeat_mask(X86_FEATURE_SSE) ) data |= X86_CR4_OSXMMEXCPT; if ( ecx & cpufeat_mask(X86_FEATURE_VMXE) ) data |= X86_CR4_VMXE; --- a/xen/include/asm-x86/amd.h +++ b/xen/include/asm-x86/amd.h @@ -22,7 +22,7 @@ cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) | \ cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_CLFLUSH)| \ cpufeat_mask(X86_FEATURE_MMX) | cpufeat_mask(X86_FEATURE_FXSR) | \ - cpufeat_mask(X86_FEATURE_XMM) | cpufeat_mask(X86_FEATURE_XMM2)) + cpufeat_mask(X86_FEATURE_SSE) | cpufeat_mask(X86_FEATURE_SSE2)) #define AMD_EXTFEATURES_K8_REV_C_ECX 0 #define AMD_EXTFEATURES_K8_REV_C_EDX ( \ cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) | \ @@ -48,7 +48,7 @@ /* Family 0Fh, Revision E */ #define AMD_FEATURES_K8_REV_E_ECX (AMD_FEATURES_K8_REV_D_ECX | \ - cpufeat_mask(X86_FEATURE_XMM3)) + cpufeat_mask(X86_FEATURE_SSE3)) #define AMD_FEATURES_K8_REV_E_EDX (AMD_FEATURES_K8_REV_D_EDX | \ cpufeat_mask(X86_FEATURE_HT)) #define AMD_EXTFEATURES_K8_REV_E_ECX (AMD_EXTFEATURES_K8_REV_D_ECX |\ --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -38,8 +38,8 @@ #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */ /* of FPU context), and CR4.OSFXSR available */ -#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */ -#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */ +#define X86_FEATURE_SSE (0*32+25) /* Streaming SIMD Extensions */ +#define X86_FEATURE_SSE2 (0*32+26) /* Streaming SIMD Extensions-2 */ #define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */ #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ #define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */ @@ -78,7 +78,7 @@ #define X86_FEATURE_APERFMPERF (3*32+16) /* APERFMPERF */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ -#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ +#define X86_FEATURE_SSE3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ #define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* Carry-less mulitplication */ #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */ #define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */ @@ -183,7 +183,9 @@ #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) #define cpu_has_mtrr 1 #define cpu_has_mmx 1 -#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) +#define cpu_has_sse boot_cpu_has(X86_FEATURE_SSE) +#define cpu_has_sse2 boot_cpu_has(X86_FEATURE_SSE2) +#define cpu_has_sse3 boot_cpu_has(X86_FEATURE_SSE3) #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) #define cpu_has_mp 1 #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -205,12 +205,12 @@ static void __init early_cpu_detect(void c->x86_model += ((eax >> 16) & 0xF) << 4; c->x86_mask = eax & 15; edx &= ~cleared_caps[cpufeat_word(X86_FEATURE_FPU)]; - ecx &= ~cleared_caps[cpufeat_word(X86_FEATURE_XMM3)]; + ecx &= ~cleared_caps[cpufeat_word(X86_FEATURE_SSE3)]; if (edx & cpufeat_mask(X86_FEATURE_CLFLUSH)) c->x86_cache_alignment = ((ebx >> 8) & 0xff) * 8; /* Leaf 0x1 capabilities filled in early for Xen. */ c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = edx; - c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] = ecx; + c->x86_capability[cpufeat_word(X86_FEATURE_SSE3)] = ecx; if ( cpuid_eax(0x80000000) >= 0x80000008 ) paddr_bits = cpuid_eax(0x80000008) & 0xff; @@ -249,7 +249,7 @@ static void generic_identify(struct cpui c->cpuid_level = cpuid_eax(0); cpuid(0x00000001, &eax, &ebx, &ecx, &edx); c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = edx; - c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] = ecx; + c->x86_capability[cpufeat_word(X86_FEATURE_SSE3)] = ecx; if ( cpu_has(c, X86_FEATURE_CLFLUSH) ) c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8; --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -2029,7 +2029,7 @@ unsigned long hvm_cr4_guest_reserved_bit X86_CR4_PCE | (leaf1_edx & cpufeat_mask(X86_FEATURE_FXSR) ? X86_CR4_OSFXSR : 0) | - (leaf1_edx & cpufeat_mask(X86_FEATURE_XMM) ? + (leaf1_edx & cpufeat_mask(X86_FEATURE_SSE) ? X86_CR4_OSXMMEXCPT : 0) | ((restore || nestedhvm_enabled(v->domain)) && (leaf1_ecx & cpufeat_mask(X86_FEATURE_VMXE)) ? --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1963,7 +1963,7 @@ int nvmx_msr_read_intercept(unsigned int data |= X86_CR4_PGE; if ( edx & cpufeat_mask(X86_FEATURE_FXSR) ) data |= X86_CR4_OSFXSR; - if ( edx & cpufeat_mask(X86_FEATURE_XMM) ) + if ( edx & cpufeat_mask(X86_FEATURE_SSE) ) data |= X86_CR4_OSXMMEXCPT; if ( ecx & cpufeat_mask(X86_FEATURE_VMXE) ) data |= X86_CR4_VMXE; --- a/xen/include/asm-x86/amd.h +++ b/xen/include/asm-x86/amd.h @@ -22,7 +22,7 @@ cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) | \ cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_CLFLUSH)| \ cpufeat_mask(X86_FEATURE_MMX) | cpufeat_mask(X86_FEATURE_FXSR) | \ - cpufeat_mask(X86_FEATURE_XMM) | cpufeat_mask(X86_FEATURE_XMM2)) + cpufeat_mask(X86_FEATURE_SSE) | cpufeat_mask(X86_FEATURE_SSE2)) #define AMD_EXTFEATURES_K8_REV_C_ECX 0 #define AMD_EXTFEATURES_K8_REV_C_EDX ( \ cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) | \ @@ -48,7 +48,7 @@ /* Family 0Fh, Revision E */ #define AMD_FEATURES_K8_REV_E_ECX (AMD_FEATURES_K8_REV_D_ECX | \ - cpufeat_mask(X86_FEATURE_XMM3)) + cpufeat_mask(X86_FEATURE_SSE3)) #define AMD_FEATURES_K8_REV_E_EDX (AMD_FEATURES_K8_REV_D_EDX | \ cpufeat_mask(X86_FEATURE_HT)) #define AMD_EXTFEATURES_K8_REV_E_ECX (AMD_EXTFEATURES_K8_REV_D_ECX |\ --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -38,8 +38,8 @@ #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */ /* of FPU context), and CR4.OSFXSR available */ -#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */ -#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */ +#define X86_FEATURE_SSE (0*32+25) /* Streaming SIMD Extensions */ +#define X86_FEATURE_SSE2 (0*32+26) /* Streaming SIMD Extensions-2 */ #define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */ #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ #define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */ @@ -78,7 +78,7 @@ #define X86_FEATURE_APERFMPERF (3*32+16) /* APERFMPERF */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ -#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ +#define X86_FEATURE_SSE3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ #define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* Carry-less mulitplication */ #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */ #define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */ @@ -183,7 +183,9 @@ #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) #define cpu_has_mtrr 1 #define cpu_has_mmx 1 -#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) +#define cpu_has_sse boot_cpu_has(X86_FEATURE_SSE) +#define cpu_has_sse2 boot_cpu_has(X86_FEATURE_SSE2) +#define cpu_has_sse3 boot_cpu_has(X86_FEATURE_SSE3) #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) #define cpu_has_mp 1 #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)