From patchwork Fri Mar 11 17:34:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 8568211 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8F3349F1C0 for ; Fri, 11 Mar 2016 17:36:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 81DCF20259 for ; Fri, 11 Mar 2016 17:36:57 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6C3D720253 for ; Fri, 11 Mar 2016 17:36:56 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1aeQxM-0004Fg-0g; Fri, 11 Mar 2016 17:34:32 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1aeQxK-0004FO-EY for xen-devel@lists.xenproject.org; Fri, 11 Mar 2016 17:34:30 +0000 Received: from [193.109.254.147] by server-4.bemta-14.messagelabs.com id 19/32-03301-5A103E65; Fri, 11 Mar 2016 17:34:29 +0000 X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-15.tower-27.messagelabs.com!1457717667!30565813!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.11; banners=-,-,- X-VirusChecked: Checked Received: (qmail 49835 invoked from network); 11 Mar 2016 17:34:28 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-15.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 11 Mar 2016 17:34:28 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Fri, 11 Mar 2016 10:34:26 -0700 Message-Id: <56E30FB402000078000DBB8F@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Fri, 11 Mar 2016 10:34:28 -0700 From: "Jan Beulich" To: "xen-devel" References: <56E30EA102000078000DBB7F@prv-mh.provo.novell.com> In-Reply-To: <56E30EA102000078000DBB7F@prv-mh.provo.novell.com> Mime-Version: 1.0 Cc: Andrew Cooper , Keir Fraser Subject: [Xen-devel] [PATCH 2/3] x86emul: check host features alongside guest ones where needed X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Jan Beulich x86emul: check host features alongside guest ones where needed Signed-off-by: Jan Beulich --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1093,6 +1093,22 @@ static bool_t vcpu_has( #define vcpu_must_have_cx16() vcpu_must_have(0x00000001, ECX, 13) #define vcpu_must_have_avx() vcpu_must_have(0x00000001, ECX, 28) +#ifdef __XEN__ +/* + * Note the (subtle?) difference between vcpu_must_have_() and + * vcpu_must_have(): The former only checks guest feature flags, + * while the latter also checks host ones, i.e. is required to be used when + * emulation code is using the same instruction class for carrying out the + * actual operation). + */ +#define host_and_vcpu_must_have(feat) ({ \ + generate_exception_if(!cpu_has_##feat, EXC_UD, -1); \ + vcpu_must_have_##feat(); \ +}) +#else +#define host_and_vcpu_must_have(feat) vcpu_must_have_##feat() +#endif + static int in_longmode( struct x86_emulate_ctxt *ctxt, @@ -3102,7 +3118,7 @@ x86_emulate( emulate_fpu_insn_memsrc("fildl", src.val); break; case 1: /* fisttp m32i */ - vcpu_must_have_sse3(); + host_and_vcpu_must_have(sse3); ea.bytes = 4; dst = ea; dst.type = OP_MEM; @@ -3211,7 +3227,7 @@ x86_emulate( emulate_fpu_insn_memsrc("fldl", src.val); break; case 1: /* fisttp m64i */ - vcpu_must_have_sse3(); + host_and_vcpu_must_have(sse3); ea.bytes = 8; dst = ea; dst.type = OP_MEM; @@ -3319,7 +3335,7 @@ x86_emulate( emulate_fpu_insn_memsrc("filds", src.val); break; case 1: /* fisttp m16i */ - vcpu_must_have_sse3(); + host_and_vcpu_must_have(sse3); ea.bytes = 2; dst = ea; dst.type = OP_MEM; @@ -4115,9 +4131,9 @@ x86_emulate( if ( vex.opcx == vex_none ) { if ( vex.pfx & VEX_PREFIX_DOUBLE_MASK ) - vcpu_must_have_sse2(); + host_and_vcpu_must_have(sse2); else - vcpu_must_have_sse(); + host_and_vcpu_must_have(sse); ea.bytes = 16; SET_SSE_PREFIX(buf[0], vex.pfx); get_fpu(X86EMUL_FPU_xmm, &fic); @@ -4128,7 +4144,7 @@ x86_emulate( ((vex.reg != 0xf) && ((ea.type == OP_MEM) || !(vex.pfx & VEX_PREFIX_SCALAR_MASK)))); - vcpu_must_have_avx(); + host_and_vcpu_must_have(avx); get_fpu(X86EMUL_FPU_ymm, &fic); ea.bytes = 16 << vex.l; } @@ -4361,16 +4377,16 @@ x86_emulate( { case vex_66: case vex_f3: - vcpu_must_have_sse2(); + host_and_vcpu_must_have(sse2); buf[0] = 0x66; /* movdqa */ get_fpu(X86EMUL_FPU_xmm, &fic); ea.bytes = 16; break; case vex_none: if ( b != 0xe7 ) - vcpu_must_have_mmx(); + host_and_vcpu_must_have(mmx); else - vcpu_must_have_sse(); + host_and_vcpu_must_have(sse); get_fpu(X86EMUL_FPU_mmx, &fic); ea.bytes = 8; break; @@ -4382,7 +4398,7 @@ x86_emulate( { fail_if((vex.opcx != vex_0f) || (vex.reg != 0xf) || ((vex.pfx != vex_66) && (vex.pfx != vex_f3))); - vcpu_must_have_avx(); + host_and_vcpu_must_have(avx); get_fpu(X86EMUL_FPU_ymm, &fic); ea.bytes = 16 << vex.l; } @@ -4688,7 +4704,7 @@ x86_emulate( generate_exception_if((modrm_reg & 7) != 1, EXC_UD, -1); generate_exception_if(ea.type != OP_MEM, EXC_UD, -1); if ( op_bytes == 8 ) - vcpu_must_have_cx16(); + host_and_vcpu_must_have(cx16); op_bytes *= 2; /* Get actual old value. */ --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1093,6 +1093,22 @@ static bool_t vcpu_has( #define vcpu_must_have_cx16() vcpu_must_have(0x00000001, ECX, 13) #define vcpu_must_have_avx() vcpu_must_have(0x00000001, ECX, 28) +#ifdef __XEN__ +/* + * Note the (subtle?) difference between vcpu_must_have_() and + * vcpu_must_have(): The former only checks guest feature flags, + * while the latter also checks host ones, i.e. is required to be used when + * emulation code is using the same instruction class for carrying out the + * actual operation). + */ +#define host_and_vcpu_must_have(feat) ({ \ + generate_exception_if(!cpu_has_##feat, EXC_UD, -1); \ + vcpu_must_have_##feat(); \ +}) +#else +#define host_and_vcpu_must_have(feat) vcpu_must_have_##feat() +#endif + static int in_longmode( struct x86_emulate_ctxt *ctxt, @@ -3102,7 +3118,7 @@ x86_emulate( emulate_fpu_insn_memsrc("fildl", src.val); break; case 1: /* fisttp m32i */ - vcpu_must_have_sse3(); + host_and_vcpu_must_have(sse3); ea.bytes = 4; dst = ea; dst.type = OP_MEM; @@ -3211,7 +3227,7 @@ x86_emulate( emulate_fpu_insn_memsrc("fldl", src.val); break; case 1: /* fisttp m64i */ - vcpu_must_have_sse3(); + host_and_vcpu_must_have(sse3); ea.bytes = 8; dst = ea; dst.type = OP_MEM; @@ -3319,7 +3335,7 @@ x86_emulate( emulate_fpu_insn_memsrc("filds", src.val); break; case 1: /* fisttp m16i */ - vcpu_must_have_sse3(); + host_and_vcpu_must_have(sse3); ea.bytes = 2; dst = ea; dst.type = OP_MEM; @@ -4115,9 +4131,9 @@ x86_emulate( if ( vex.opcx == vex_none ) { if ( vex.pfx & VEX_PREFIX_DOUBLE_MASK ) - vcpu_must_have_sse2(); + host_and_vcpu_must_have(sse2); else - vcpu_must_have_sse(); + host_and_vcpu_must_have(sse); ea.bytes = 16; SET_SSE_PREFIX(buf[0], vex.pfx); get_fpu(X86EMUL_FPU_xmm, &fic); @@ -4128,7 +4144,7 @@ x86_emulate( ((vex.reg != 0xf) && ((ea.type == OP_MEM) || !(vex.pfx & VEX_PREFIX_SCALAR_MASK)))); - vcpu_must_have_avx(); + host_and_vcpu_must_have(avx); get_fpu(X86EMUL_FPU_ymm, &fic); ea.bytes = 16 << vex.l; } @@ -4361,16 +4377,16 @@ x86_emulate( { case vex_66: case vex_f3: - vcpu_must_have_sse2(); + host_and_vcpu_must_have(sse2); buf[0] = 0x66; /* movdqa */ get_fpu(X86EMUL_FPU_xmm, &fic); ea.bytes = 16; break; case vex_none: if ( b != 0xe7 ) - vcpu_must_have_mmx(); + host_and_vcpu_must_have(mmx); else - vcpu_must_have_sse(); + host_and_vcpu_must_have(sse); get_fpu(X86EMUL_FPU_mmx, &fic); ea.bytes = 8; break; @@ -4382,7 +4398,7 @@ x86_emulate( { fail_if((vex.opcx != vex_0f) || (vex.reg != 0xf) || ((vex.pfx != vex_66) && (vex.pfx != vex_f3))); - vcpu_must_have_avx(); + host_and_vcpu_must_have(avx); get_fpu(X86EMUL_FPU_ymm, &fic); ea.bytes = 16 << vex.l; } @@ -4688,7 +4704,7 @@ x86_emulate( generate_exception_if((modrm_reg & 7) != 1, EXC_UD, -1); generate_exception_if(ea.type != OP_MEM, EXC_UD, -1); if ( op_bytes == 8 ) - vcpu_must_have_cx16(); + host_and_vcpu_must_have(cx16); op_bytes *= 2; /* Get actual old value. */