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Tue, 22 Mar 2016 07:05:56 -0600 Message-Id: <56F1514302000078000DF2CD@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Tue, 22 Mar 2016 07:05:55 -0600 From: "Jan Beulich" To: "xen-devel" Mime-Version: 1.0 Cc: Andrew Cooper , Wei Liu , Ian Jackson , Stefano Stabellini Subject: [Xen-devel] [PATCH] libxc/x86: XSAVE related adjustments X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP - don't unintentionally increase features reported by sub-leaf 0 EDX:EAX - don't discard the known flags in sub-leaves 2..63 ECX - handle components 32...62 (EDX) in sub-leaf 1 consistently with 0...31 (ECX) - zap sub-leaves beyond 62 Signed-off-by: Jan Beulich --- While obviously requiring re-basing on either end when taking Andrew's CPUID levelling series into account, the changes done here appear to be orthogonal to those done in his series. libxc/x86: XSAVE related adjustments - don't unintentionally increase features reported by sub-leaf 0 EDX:EAX - don't discard the known flags in sub-leaves 2..63 ECX - handle components 32...62 (EDX) in sub-leaf 1 consistently with 0...31 (ECX) - zap sub-leaves beyond 62 Signed-off-by: Jan Beulich --- While obviously requiring re-basing on either end when taking Andrew's CPUID levelling series into account, the changes done here appear to be orthogonal to those done in his series. --- a/tools/libxc/xc_cpuid_x86.c +++ b/tools/libxc/xc_cpuid_x86.c @@ -281,10 +281,14 @@ static void intel_xc_cpuid_policy(xc_int } } +/* Leaf 1, EAX: */ #define XSAVEOPT (1 << 0) #define XSAVEC (1 << 1) #define XGETBV1 (1 << 2) #define XSAVES (1 << 3) +/* Leaves beyond 1, ECX: */ +#define XSTATE_XSS (1 << 0) +#define XSTATE_ALIGN64 (1 << 1) /* Configure extended state enumeration leaves (0x0000000D for xsave) */ static void xc_cpuid_config_xsave(xc_interface *xch, const struct cpuid_domain_info *info, @@ -300,9 +304,9 @@ static void xc_cpuid_config_xsave(xc_int { case 0: /* EAX: low 32bits of xfeature_enabled_mask */ - regs[0] = info->xfeature_mask & 0xFFFFFFFF; + regs[0] &= info->xfeature_mask; /* EDX: high 32bits of xfeature_enabled_mask */ - regs[3] = (info->xfeature_mask >> 32) & 0xFFFFFFFF; + regs[3] &= info->xfeature_mask >> 32; /* ECX: max size required by all HW features */ { unsigned int _input[2] = {0xd, 0x0}, _regs[4]; @@ -325,16 +329,20 @@ static void xc_cpuid_config_xsave(xc_int if ( !info->hvm ) regs[0] &= ~XSAVES; regs[2] &= info->xfeature_mask; - regs[3] = 0; + regs[3] &= info->xfeature_mask >> 32; break; - case 2 ... 63: /* sub-leaves */ + case 2 ... 62: /* per-component sub-leaves */ if ( !(info->xfeature_mask & (1ULL << input[1])) ) { regs[0] = regs[1] = regs[2] = regs[3] = 0; break; } /* Don't touch EAX, EBX. Also cleanup ECX and EDX */ - regs[2] = regs[3] = 0; + regs[2] &= XSTATE_XSS | XSTATE_ALIGN64; + regs[3] = 0; + break; + default: + regs[0] = regs[1] = regs[2] = regs[3] = 0; break; } } --- a/tools/libxc/xc_cpuid_x86.c +++ b/tools/libxc/xc_cpuid_x86.c @@ -281,10 +281,14 @@ static void intel_xc_cpuid_policy(xc_int } } +/* Leaf 1, EAX: */ #define XSAVEOPT (1 << 0) #define XSAVEC (1 << 1) #define XGETBV1 (1 << 2) #define XSAVES (1 << 3) +/* Leaves beyond 1, ECX: */ +#define XSTATE_XSS (1 << 0) +#define XSTATE_ALIGN64 (1 << 1) /* Configure extended state enumeration leaves (0x0000000D for xsave) */ static void xc_cpuid_config_xsave(xc_interface *xch, const struct cpuid_domain_info *info, @@ -300,9 +304,9 @@ static void xc_cpuid_config_xsave(xc_int { case 0: /* EAX: low 32bits of xfeature_enabled_mask */ - regs[0] = info->xfeature_mask & 0xFFFFFFFF; + regs[0] &= info->xfeature_mask; /* EDX: high 32bits of xfeature_enabled_mask */ - regs[3] = (info->xfeature_mask >> 32) & 0xFFFFFFFF; + regs[3] &= info->xfeature_mask >> 32; /* ECX: max size required by all HW features */ { unsigned int _input[2] = {0xd, 0x0}, _regs[4]; @@ -325,16 +329,20 @@ static void xc_cpuid_config_xsave(xc_int if ( !info->hvm ) regs[0] &= ~XSAVES; regs[2] &= info->xfeature_mask; - regs[3] = 0; + regs[3] &= info->xfeature_mask >> 32; break; - case 2 ... 63: /* sub-leaves */ + case 2 ... 62: /* per-component sub-leaves */ if ( !(info->xfeature_mask & (1ULL << input[1])) ) { regs[0] = regs[1] = regs[2] = regs[3] = 0; break; } /* Don't touch EAX, EBX. Also cleanup ECX and EDX */ - regs[2] = regs[3] = 0; + regs[2] &= XSTATE_XSS | XSTATE_ALIGN64; + regs[3] = 0; + break; + default: + regs[0] = regs[1] = regs[2] = regs[3] = 0; break; } }