From patchwork Mon May 2 15:11:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 8993111 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2D8C2BF29F for ; Mon, 2 May 2016 15:14:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E836A201DD for ; Mon, 2 May 2016 15:14:08 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CEDDA20165 for ; Mon, 2 May 2016 15:14:07 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1axFVm-00026X-DG; Mon, 02 May 2016 15:11:50 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1axFVl-00026R-EF for xen-devel@lists.xenproject.org; Mon, 02 May 2016 15:11:49 +0000 Received: from [85.158.139.211] by server-14.bemta-5.messagelabs.com id 76/C0-30904-43E67275; Mon, 02 May 2016 15:11:48 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIIsWRWlGSWpSXmKPExsXS6fjDS9c4Tz3 c4MVbE4vvWyYzOTB6HP5whSWAMYo1My8pvyKBNWPVz63MBe8cKnZc2c/ewDjJuIuRg0NIIE9i 89xEEJNXwE7i+XGNLkZODgkBQ4l981exgdgsAqoS3RubWEBsNgF1ibZn21lBykUEDCTOHU0CC TMLBErcuj+DEcQWFjCWeH/oCBPEREGJvzuEIUrsJB7fbGKbwMg1CyEzC0kGwtaSePjrFguErS 2xbOFrZpByZgFpieX/OCBMS4mW3aGoKkBsF4nW9vusCxg5VjGqF6cWlaUW6ZroJRVlpmeU5CZ m5ugaGpjq5aYWFyemp+YkJhXrJefnbmIEBh0DEOxgvNXnfIhRkoNJSZR3UpZ6uBBfUn5KZUZi cUZ8UWlOavEhRhkODiUJXrdcoJxgUWp6akVaZg4w/GHSEhw8SiK84SBp3uKCxNzizHSI1ClGR SlxXjaQhABIIqM0D64NFnOXGGWlhHkZgQ4R4ilILcrNLEGVf8UozsGoJMxrBzKFJzOvBG76K6 DFTECLs9ergiwuSURISTUwtn29X7Jtd7r39RSf2j2T9qxp7vRilxGX+7OKKUZUbvHnp28tivR vB94tiDvmEHeX++uy/vS5frESjD3nw9jbbEzXVWq9n3q/5E1l/xIF89La4on+0rMtzp/NVb0+ 17lm9/sbx9u3q97pyDhXuOnWHzvWjSrMys97ztllL9ykeEZIyHyGn8MVJZbijERDLeai4kQA/ mm2arQCAAA= X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-12.tower-206.messagelabs.com!1462201905!1073785!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 8.34; banners=-,-,- X-VirusChecked: Checked Received: (qmail 48304 invoked from network); 2 May 2016 15:11:47 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-12.tower-206.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 2 May 2016 15:11:47 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Mon, 02 May 2016 09:11:44 -0600 Message-Id: <57278A4D02000078000E7B8B@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Mon, 02 May 2016 09:11:41 -0600 From: "Jan Beulich" To: "xen-devel" Mime-Version: 1.0 Cc: Andrew Cooper , Wei Liu Subject: [Xen-devel] [PATCH] x86: cap address bits CPUID output X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Don't use more or report more to guests than we are capable of handling. At once simplify the code in hvm_cpuid() and mtrr_top_of_ram(). Signed-off-by: Jan Beulich x86: cap address bits CPUID output Don't use more or report more to guests than we are capable of handling. At once simplify the code in hvm_cpuid() and mtrr_top_of_ram(). Signed-off-by: Jan Beulich --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -46,6 +46,7 @@ const struct cpu_dev *__read_mostly cpu_ unsigned int paddr_bits __read_mostly = 36; unsigned int hap_paddr_bits __read_mostly = 36; +unsigned int vaddr_bits __read_mostly = VADDR_BITS; /* * Default host IA32_CR_PAT value to cover all memory types. @@ -240,7 +241,14 @@ static void __init early_cpu_detect(void if ( cpuid_eax(0x80000000) >= 0x80000008 ) { eax = cpuid_eax(0x80000008); paddr_bits = eax & 0xff; + if (paddr_bits > PADDR_BITS) + paddr_bits = PADDR_BITS; + vaddr_bits = (eax >> 8) & 0xff; + if (vaddr_bits > VADDR_BITS) + vaddr_bits = VADDR_BITS; hap_paddr_bits = ((eax >> 16) & 0xff) ?: paddr_bits; + if (hap_paddr_bits > PADDR_BITS) + hap_paddr_bits = PADDR_BITS; } } --- a/xen/arch/x86/e820.c +++ b/xen/arch/x86/e820.c @@ -451,11 +451,11 @@ static uint64_t __init mtrr_top_of_ram(v return 0; /* Find the physical address size for this CPU. */ - cpuid(0x80000000, &eax, &ebx, &ecx, &edx); - if ( eax >= 0x80000008 ) + if ( cpuid_eax(0x80000000) >= 0x80000008 ) { - cpuid(0x80000008, &eax, &ebx, &ecx, &edx); - phys_bits = (uint8_t)eax; + phys_bits = (uint8_t)cpuid_eax(0x80000008); + if ( phys_bits > PADDR_BITS ) + phys_bits = PADDR_BITS; } addr_mask = ((1ull << phys_bits) - 1) & ~((1ull << 12) - 1); --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -3504,19 +3504,19 @@ void hvm_cpuid(unsigned int input, unsig break; case 0x80000008: + *eax &= 0xff; count = d->arch.paging.gfn_bits + PAGE_SHIFT; - if ( (*eax & 0xff) > count ) - *eax = (*eax & ~0xff) | count; + if ( *eax > count ) + *eax = count; hvm_cpuid(1, NULL, NULL, NULL, &_edx); count = _edx & (cpufeat_mask(X86_FEATURE_PAE) | cpufeat_mask(X86_FEATURE_PSE36)) ? 36 : 32; - if ( (*eax & 0xff) < count ) - *eax = (*eax & ~0xff) | count; + if ( *eax < count ) + *eax = count; hvm_cpuid(0x80000001, NULL, NULL, NULL, &_edx); - *eax = (*eax & ~0xffff00) | (_edx & cpufeat_mask(X86_FEATURE_LM) - ? 0x3000 : 0x2000); + *eax |= _edx & cpufeat_mask(X86_FEATURE_LM) ? vaddr_bits << 8 : 0x2000; *ebx &= hvm_featureset[FEATURESET_e8b]; break; --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1146,6 +1146,7 @@ void pv_cpuid(struct cpu_user_regs *regs break; case 0x80000008: + a = paddr_bits | (vaddr_bits << 8); b &= pv_featureset[FEATURESET_e8b]; break; --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -216,10 +216,12 @@ extern bool_t opt_cpu_info; extern u32 cpuid_ext_features; extern u64 trampoline_misc_enable_off; -/* Maximum width of physical addresses supported by the hardware */ +/* Maximum width of physical addresses supported by the hardware. */ extern unsigned int paddr_bits; -/* Max physical address width supported within HAP guests */ +/* Max physical address width supported within HAP guests. */ extern unsigned int hap_paddr_bits; +/* Maximum width of virtual addresses supported by the hardware. */ +extern unsigned int vaddr_bits; extern const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id table[]); --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -46,6 +46,7 @@ const struct cpu_dev *__read_mostly cpu_ unsigned int paddr_bits __read_mostly = 36; unsigned int hap_paddr_bits __read_mostly = 36; +unsigned int vaddr_bits __read_mostly = VADDR_BITS; /* * Default host IA32_CR_PAT value to cover all memory types. @@ -240,7 +241,14 @@ static void __init early_cpu_detect(void if ( cpuid_eax(0x80000000) >= 0x80000008 ) { eax = cpuid_eax(0x80000008); paddr_bits = eax & 0xff; + if (paddr_bits > PADDR_BITS) + paddr_bits = PADDR_BITS; + vaddr_bits = (eax >> 8) & 0xff; + if (vaddr_bits > VADDR_BITS) + vaddr_bits = VADDR_BITS; hap_paddr_bits = ((eax >> 16) & 0xff) ?: paddr_bits; + if (hap_paddr_bits > PADDR_BITS) + hap_paddr_bits = PADDR_BITS; } } --- a/xen/arch/x86/e820.c +++ b/xen/arch/x86/e820.c @@ -451,11 +451,11 @@ static uint64_t __init mtrr_top_of_ram(v return 0; /* Find the physical address size for this CPU. */ - cpuid(0x80000000, &eax, &ebx, &ecx, &edx); - if ( eax >= 0x80000008 ) + if ( cpuid_eax(0x80000000) >= 0x80000008 ) { - cpuid(0x80000008, &eax, &ebx, &ecx, &edx); - phys_bits = (uint8_t)eax; + phys_bits = (uint8_t)cpuid_eax(0x80000008); + if ( phys_bits > PADDR_BITS ) + phys_bits = PADDR_BITS; } addr_mask = ((1ull << phys_bits) - 1) & ~((1ull << 12) - 1); --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -3504,19 +3504,19 @@ void hvm_cpuid(unsigned int input, unsig break; case 0x80000008: + *eax &= 0xff; count = d->arch.paging.gfn_bits + PAGE_SHIFT; - if ( (*eax & 0xff) > count ) - *eax = (*eax & ~0xff) | count; + if ( *eax > count ) + *eax = count; hvm_cpuid(1, NULL, NULL, NULL, &_edx); count = _edx & (cpufeat_mask(X86_FEATURE_PAE) | cpufeat_mask(X86_FEATURE_PSE36)) ? 36 : 32; - if ( (*eax & 0xff) < count ) - *eax = (*eax & ~0xff) | count; + if ( *eax < count ) + *eax = count; hvm_cpuid(0x80000001, NULL, NULL, NULL, &_edx); - *eax = (*eax & ~0xffff00) | (_edx & cpufeat_mask(X86_FEATURE_LM) - ? 0x3000 : 0x2000); + *eax |= _edx & cpufeat_mask(X86_FEATURE_LM) ? vaddr_bits << 8 : 0x2000; *ebx &= hvm_featureset[FEATURESET_e8b]; break; --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1146,6 +1146,7 @@ void pv_cpuid(struct cpu_user_regs *regs break; case 0x80000008: + a = paddr_bits | (vaddr_bits << 8); b &= pv_featureset[FEATURESET_e8b]; break; --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -216,10 +216,12 @@ extern bool_t opt_cpu_info; extern u32 cpuid_ext_features; extern u64 trampoline_misc_enable_off; -/* Maximum width of physical addresses supported by the hardware */ +/* Maximum width of physical addresses supported by the hardware. */ extern unsigned int paddr_bits; -/* Max physical address width supported within HAP guests */ +/* Max physical address width supported within HAP guests. */ extern unsigned int hap_paddr_bits; +/* Maximum width of virtual addresses supported by the hardware. */ +extern unsigned int vaddr_bits; extern const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id table[]);