From patchwork Wed Jun 8 13:50:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 9164747 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1107F60572 for ; Wed, 8 Jun 2016 13:52:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F3DC8281FE for ; Wed, 8 Jun 2016 13:52:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E8BC4282DC; Wed, 8 Jun 2016 13:52:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 38FAB281FE for ; Wed, 8 Jun 2016 13:52:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAdsf-0006jn-CQ; Wed, 08 Jun 2016 13:50:49 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAdsd-0006jY-S9 for xen-devel@lists.xenproject.org; Wed, 08 Jun 2016 13:50:47 +0000 Received: from [193.109.254.147] by server-10.bemta-14.messagelabs.com id 89/74-31433-7B228575; Wed, 08 Jun 2016 13:50:47 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrGIsWRWlGSWpSXmKPExsXS6fjDS3ebUkS 4weEdTBbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8b3i6eZC5aFVvx7dIq9gXGSZxcjJ4eQQJ7E jw23WEFsXgE7iaULuxhBbAkBQ4l981exdTFycLAIqEpsuRgMEmYTUJdoe7adFSQsImAgce5oE ojJLKAvsW0dC0iFMFB0y4bdTBDD7STu3XvNDmJzCthLPN63FayTV0BQ4u8OYZAwM1DJqmk/mS cw8sxCyMxCkoGwtSQe/rrFAmFrSyxb+Jp5FtheaYnl/zggwpYSl/63sKEqAbFdJBrWP2JfwMi xilG9OLWoLLVI10QvqSgzPaMkNzEzR9fQ0EQvN7W4ODE9NScxqVgvOT93EyMwTBmAYAfjioXO hxglOZiURHkV3cPDhfiS8lMqMxKLM+KLSnNSiw8xanBwCGzbtfoCoxRLXn5eqpIEb4liRLiQY FFqempFWmYOMJJgSiU4eJREeLtB0rzFBYm5xZnpEKlTjIpS4rw2IAkBkERGaR5cGyx6LzHKSg nzMgIdJcRTkFqUm1mCKv+KUZyDUUmYNxFkCk9mXgnc9FdAi5mAFi8/Eg6yuCQRISXVwCgleXF TlMjEh+8EF5/5/fFRzbW9Uoctn9/cVnJsRVLy62sHEu9yi3DulefZzfSfM/pg45dLUtP6Wwq3 Vh7+15hvGGxRudCs/d7S6/+8r9zPklxR8TZGkWGB+drn+z6wSNxZ+urVgid/9+ctKxVfuTF7r lN0v4+A2YWLgs+4hGafs/k2/92q3mY/JZbijERDLeai4kQAh0EwxdkCAAA= X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-13.tower-27.messagelabs.com!1465393843!46569542!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 14910 invoked from network); 8 Jun 2016 13:50:45 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-13.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 8 Jun 2016 13:50:45 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Wed, 08 Jun 2016 07:50:43 -0600 Message-Id: <57583ECF02000078000F3205@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Wed, 08 Jun 2016 07:50:39 -0600 From: "Jan Beulich" To: "xen-devel" References: <57583E0D02000078000F31F2@prv-mh.provo.novell.com> In-Reply-To: <57583E0D02000078000F31F2@prv-mh.provo.novell.com> Mime-Version: 1.0 Cc: Andrew Cooper Subject: [Xen-devel] [PATCH 3/5] mwait-idle: add BXT support X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Broxton has all the HSW C-states, except C3. BXT C-state timing is slightly different. Here we trust the IRTL MSRs as authority on maximum C-state latency, and override the driver's tables with the values found in the associated IRTL MSRs. Further we set the target_residency to 1x maximum latency, trusting the hardware demotion logic. Signed-off-by: Len Brown [Linux commit: 5dcef694860100fd16885f052591b1268b764d21] Signed-off-by: Jan Beulich mwait-idle: add BXT support Broxton has all the HSW C-states, except C3. BXT C-state timing is slightly different. Here we trust the IRTL MSRs as authority on maximum C-state latency, and override the driver's tables with the values found in the associated IRTL MSRs. Further we set the target_residency to 1x maximum latency, trusting the hardware demotion logic. Signed-off-by: Len Brown [Linux commit: 5dcef694860100fd16885f052591b1268b764d21] Signed-off-by: Jan Beulich --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -612,6 +612,52 @@ static const struct cpuidle_state knl_cs {} }; +static struct cpuidle_state bxt_cstates[] = { + { + .name = "C1-BXT", + .flags = MWAIT2flg(0x00), + .exit_latency = 2, + .target_residency = 2, + }, + { + .name = "C1E-BXT", + .flags = MWAIT2flg(0x01), + .exit_latency = 10, + .target_residency = 20, + }, + { + .name = "C6-BXT", + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 133, + .target_residency = 133, + }, + { + .name = "C7s-BXT", + .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 155, + .target_residency = 155, + }, + { + .name = "C8-BXT", + .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 1000, + .target_residency = 1000, + }, + { + .name = "C9-BXT", + .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 2000, + .target_residency = 2000, + }, + { + .name = "C10-BXT", + .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 10000, + .target_residency = 10000, + }, + {} +}; + static void mwait_idle(void) { unsigned int cpu = smp_processor_id(); @@ -793,11 +839,16 @@ static const struct idle_cpu idle_cpu_kn .state_table = knl_cstates, }; +static const struct idle_cpu idle_cpu_bxt = { + .state_table = bxt_cstates, + .disable_promotion_to_c1e = 1, +}; + #define ICPU(model, cpu) \ { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MONITOR, \ &idle_cpu_##cpu} -static const struct x86_cpu_id intel_idle_ids[] __initconst = { +static const struct x86_cpu_id intel_idle_ids[] __initconstrel = { ICPU(0x1a, nehalem), ICPU(0x1e, nehalem), ICPU(0x1f, nehalem), @@ -829,6 +880,7 @@ static const struct x86_cpu_id intel_idl ICPU(0x9e, skl), ICPU(0x55, skx), ICPU(0x57, knl), + ICPU(0x5c, bxt), {} }; @@ -860,6 +912,72 @@ static void __init ivt_idle_state_table_ } /* + * Translate IRTL (Interrupt Response Time Limit) MSR to usec + */ + +static const unsigned int __initconst irtl_ns_units[] = { + 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; + +static unsigned long long __init irtl_2_usec(unsigned long long irtl) +{ + unsigned long long ns; + + ns = irtl_ns_units[(irtl >> 10) & 0x3]; + + return (irtl & 0x3FF) * ns / 1000; +} +/* + * bxt_idle_state_table_update(void) + * + * On BXT, we trust the IRTL to show the definitive maximum latency + * We use the same value for target_residency. + */ +static void __init bxt_idle_state_table_update(void) +{ + unsigned long long msr; + + rdmsrl(MSR_PKGC6_IRTL, msr); + if (msr) { + unsigned int usec = irtl_2_usec(msr); + + bxt_cstates[2].exit_latency = usec; + bxt_cstates[2].target_residency = usec; + } + + rdmsrl(MSR_PKGC7_IRTL, msr); + if (msr) { + unsigned int usec = irtl_2_usec(msr); + + bxt_cstates[3].exit_latency = usec; + bxt_cstates[3].target_residency = usec; + } + + rdmsrl(MSR_PKGC8_IRTL, msr); + if (msr) { + unsigned int usec = irtl_2_usec(msr); + + bxt_cstates[4].exit_latency = usec; + bxt_cstates[4].target_residency = usec; + } + + rdmsrl(MSR_PKGC9_IRTL, msr); + if (msr) { + unsigned int usec = irtl_2_usec(msr); + + bxt_cstates[5].exit_latency = usec; + bxt_cstates[5].target_residency = usec; + } + + rdmsrl(MSR_PKGC10_IRTL, msr); + if (msr) { + unsigned int usec = irtl_2_usec(msr); + + bxt_cstates[6].exit_latency = usec; + bxt_cstates[6].target_residency = usec; + } +} + +/* * sklh_idle_state_table_update(void) * * On SKL-H (model 0x5e) disable C8 and C9 if: @@ -907,6 +1025,9 @@ static void __init mwait_idle_state_tabl case 0x3e: /* IVT */ ivt_idle_state_table_update(); break; + case 0x5c: /* BXT */ + bxt_idle_state_table_update(); + break; case 0x5e: /* SKL-H */ sklh_idle_state_table_update(); break; --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -501,4 +501,12 @@ #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 +/* Interrupt Response Limit */ +#define MSR_PKGC3_IRTL 0x0000060a +#define MSR_PKGC6_IRTL 0x0000060b +#define MSR_PKGC7_IRTL 0x0000060c +#define MSR_PKGC8_IRTL 0x00000633 +#define MSR_PKGC9_IRTL 0x00000634 +#define MSR_PKGC10_IRTL 0x00000635 + #endif /* __ASM_MSR_INDEX_H */ --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -612,6 +612,52 @@ static const struct cpuidle_state knl_cs {} }; +static struct cpuidle_state bxt_cstates[] = { + { + .name = "C1-BXT", + .flags = MWAIT2flg(0x00), + .exit_latency = 2, + .target_residency = 2, + }, + { + .name = "C1E-BXT", + .flags = MWAIT2flg(0x01), + .exit_latency = 10, + .target_residency = 20, + }, + { + .name = "C6-BXT", + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 133, + .target_residency = 133, + }, + { + .name = "C7s-BXT", + .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 155, + .target_residency = 155, + }, + { + .name = "C8-BXT", + .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 1000, + .target_residency = 1000, + }, + { + .name = "C9-BXT", + .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 2000, + .target_residency = 2000, + }, + { + .name = "C10-BXT", + .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 10000, + .target_residency = 10000, + }, + {} +}; + static void mwait_idle(void) { unsigned int cpu = smp_processor_id(); @@ -793,11 +839,16 @@ static const struct idle_cpu idle_cpu_kn .state_table = knl_cstates, }; +static const struct idle_cpu idle_cpu_bxt = { + .state_table = bxt_cstates, + .disable_promotion_to_c1e = 1, +}; + #define ICPU(model, cpu) \ { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MONITOR, \ &idle_cpu_##cpu} -static const struct x86_cpu_id intel_idle_ids[] __initconst = { +static const struct x86_cpu_id intel_idle_ids[] __initconstrel = { ICPU(0x1a, nehalem), ICPU(0x1e, nehalem), ICPU(0x1f, nehalem), @@ -829,6 +880,7 @@ static const struct x86_cpu_id intel_idl ICPU(0x9e, skl), ICPU(0x55, skx), ICPU(0x57, knl), + ICPU(0x5c, bxt), {} }; @@ -860,6 +912,72 @@ static void __init ivt_idle_state_table_ } /* + * Translate IRTL (Interrupt Response Time Limit) MSR to usec + */ + +static const unsigned int __initconst irtl_ns_units[] = { + 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; + +static unsigned long long __init irtl_2_usec(unsigned long long irtl) +{ + unsigned long long ns; + + ns = irtl_ns_units[(irtl >> 10) & 0x3]; + + return (irtl & 0x3FF) * ns / 1000; +} +/* + * bxt_idle_state_table_update(void) + * + * On BXT, we trust the IRTL to show the definitive maximum latency + * We use the same value for target_residency. + */ +static void __init bxt_idle_state_table_update(void) +{ + unsigned long long msr; + + rdmsrl(MSR_PKGC6_IRTL, msr); + if (msr) { + unsigned int usec = irtl_2_usec(msr); + + bxt_cstates[2].exit_latency = usec; + bxt_cstates[2].target_residency = usec; + } + + rdmsrl(MSR_PKGC7_IRTL, msr); + if (msr) { + unsigned int usec = irtl_2_usec(msr); + + bxt_cstates[3].exit_latency = usec; + bxt_cstates[3].target_residency = usec; + } + + rdmsrl(MSR_PKGC8_IRTL, msr); + if (msr) { + unsigned int usec = irtl_2_usec(msr); + + bxt_cstates[4].exit_latency = usec; + bxt_cstates[4].target_residency = usec; + } + + rdmsrl(MSR_PKGC9_IRTL, msr); + if (msr) { + unsigned int usec = irtl_2_usec(msr); + + bxt_cstates[5].exit_latency = usec; + bxt_cstates[5].target_residency = usec; + } + + rdmsrl(MSR_PKGC10_IRTL, msr); + if (msr) { + unsigned int usec = irtl_2_usec(msr); + + bxt_cstates[6].exit_latency = usec; + bxt_cstates[6].target_residency = usec; + } +} + +/* * sklh_idle_state_table_update(void) * * On SKL-H (model 0x5e) disable C8 and C9 if: @@ -907,6 +1025,9 @@ static void __init mwait_idle_state_tabl case 0x3e: /* IVT */ ivt_idle_state_table_update(); break; + case 0x5c: /* BXT */ + bxt_idle_state_table_update(); + break; case 0x5e: /* SKL-H */ sklh_idle_state_table_update(); break; --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -501,4 +501,12 @@ #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 +/* Interrupt Response Limit */ +#define MSR_PKGC3_IRTL 0x0000060a +#define MSR_PKGC6_IRTL 0x0000060b +#define MSR_PKGC7_IRTL 0x0000060c +#define MSR_PKGC8_IRTL 0x00000633 +#define MSR_PKGC9_IRTL 0x00000634 +#define MSR_PKGC10_IRTL 0x00000635 + #endif /* __ASM_MSR_INDEX_H */