diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
index 923fe42a0b..5e660af395 100644
--- a/xen/arch/x86/cpu/vpmu_intel.c
+++ b/xen/arch/x86/cpu/vpmu_intel.c
@@ -171,6 +171,8 @@ static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index)
     case MSR_CORE_PERF_GLOBAL_CTRL:
     case MSR_CORE_PERF_GLOBAL_STATUS:
     case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+    case MSR_CORE_PERF_GLOBAL_STATUS_SET:
+    case MSR_CORE_PERF_GLOBAL_INUSE:
         *type = MSR_TYPE_GLOBAL;
         return 1;
 
@@ -545,10 +547,21 @@ static int cf_check core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content)
         core2_vpmu_cxt->global_status &= ~msr_content;
         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, msr_content);
         return 0;
+    case MSR_CORE_PERF_GLOBAL_STATUS_SET:
+        if ( (v->domain->arch.cpuid->basic.pmu_version < 4) ||
+             (msr_content & global_ovf_ctrl_mask) )
+            return -EINVAL;
+        core2_vpmu_cxt->global_status |= msr_content;
+        wrmsrl(MSR_CORE_PERF_GLOBAL_STATUS_SET, msr_content);
+        return 0;
     case MSR_CORE_PERF_GLOBAL_STATUS:
         gdprintk(XENLOG_INFO, "Can not write readonly MSR: "
                  "MSR_PERF_GLOBAL_STATUS(0x38E)!\n");
         return -EINVAL;
+    case MSR_CORE_PERF_GLOBAL_INUSE:
+        gdprintk(XENLOG_INFO, "Can not write readonly MSR: "
+                 "MSR_PERF_GLOBAL_INUSE(0x392)!\n");
+        return -EINVAL;
     case MSR_IA32_PEBS_ENABLE:
         if ( vpmu_features & (XENPMU_FEATURE_IPC_ONLY |
                               XENPMU_FEATURE_ARCH_ONLY) )
@@ -688,7 +701,8 @@ static int cf_check core2_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
         core2_vpmu_cxt = vpmu->context;
         switch ( msr )
         {
-        case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+        case MSR_CORE_PERF_GLOBAL_OVF_CTRL: /* FALLTHROUGH */
+        case MSR_CORE_PERF_GLOBAL_STATUS_SET:
             *msr_content = 0;
             break;
         case MSR_CORE_PERF_GLOBAL_STATUS:
@@ -700,6 +714,10 @@ static int cf_check core2_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
             else
                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, *msr_content);
             break;
+        case MSR_CORE_PERF_GLOBAL_INUSE:
+            if ( v->domain->arch.cpuid->basic.pmu_version < 4 )
+                return -EINVAL;
+            /* FALLTHROUGH */
         default:
             rdmsrl(msr, *msr_content);
         }
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index cd772585fe..af70ed8f30 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -3375,6 +3375,8 @@ static int cf_check vmx_msr_read_intercept(
     case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL:
     case MSR_IA32_PEBS_ENABLE:
     case MSR_IA32_DS_AREA:
+    case MSR_CORE_PERF_GLOBAL_STATUS_SET:
+    case MSR_CORE_PERF_GLOBAL_INUSE:
         if ( vpmu_do_rdmsr(msr, msr_content) )
             goto gp_fault;
         break;
@@ -3698,6 +3700,9 @@ static int cf_check vmx_msr_write_intercept(
     case MSR_IA32_PEBS_ENABLE:
     case MSR_IA32_DS_AREA:
          if ( vpmu_do_wrmsr(msr, msr_content) )
+    case MSR_CORE_PERF_GLOBAL_STATUS_SET:
+    case MSR_CORE_PERF_GLOBAL_INUSE:
+         if ( vpmu_do_wrmsr(msr, msr_content) )
             goto gp_fault;
         break;
 
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 09bfde1060..105485bb1e 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -968,6 +968,9 @@ static int cf_check read_msr(
     case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL_LAST:
     case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTRn:
     case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+    case MSR_IA32_PEBS_ENABLE:
+    case MSR_CORE_PERF_GLOBAL_STATUS_SET:
+    case MSR_CORE_PERF_GLOBAL_INUSE:
         if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
         {
             vpmu_msr = true;
@@ -1148,6 +1151,8 @@ static int cf_check write_msr(
     case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL_LAST:
     case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTRn:
     case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+    case MSR_CORE_PERF_GLOBAL_STATUS_SET:
+    case MSR_CORE_PERF_GLOBAL_INUSE:
         if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
         {
             vpmu_msr = true;
