| Message ID | 5aa05592497ba9c4d207185d81981442d43ba676.1675780434.git.oleksii.kurochko@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISCV basic exception handling implementation | expand |
On Wed, Feb 8, 2023 at 12:47 AM Oleksii Kurochko <oleksii.kurochko@gmail.com> wrote: > > The patch introduces a set of registers which should be saved to and > restored from a stack after an exception occurs and a set of defines > which will be used during exception context saving/restoring. > > Originally <asm/processor.h> header was introduced in the patch series > from Bobby so partially it was > re-used and the following changes were done: > - Move all RISCV_CPU_USER_REGS_* to asm/asm-offsets.c > - Remove RISCV_CPU_USER_REGS_OFFSET & RISCV_CPU_USER_REGS_SIZE as > there is no sense in them after RISCV_CPU_USER_REGS_* were moved to > asm/asm-offsets.c > - Remove RISCV_PCPUINFO_* as they aren't needed for current status of > the RISC-V port > - register_t renamed to unsigned long > - rename wait_for_interrupt to wfi > > Signed-off-by: Bobby Eshleman <bobby.eshleman@gmail.com> > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > Changes in V3: > - update code style for die() function > --- > Changes in V2: > - All the changes were added to the commit message. > - temporarily was added function die() to stop exectution it will be > removed after panic() will be available. > --- > xen/arch/riscv/include/asm/processor.h | 83 ++++++++++++++++++++++++++ > xen/arch/riscv/riscv64/asm-offsets.c | 53 ++++++++++++++++ > 2 files changed, 136 insertions(+) > create mode 100644 xen/arch/riscv/include/asm/processor.h > > diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/include/asm/processor.h > new file mode 100644 > index 0000000000..a71448e02e > --- /dev/null > +++ b/xen/arch/riscv/include/asm/processor.h > @@ -0,0 +1,83 @@ > +/* SPDX-License-Identifier: MIT */ > +/****************************************************************************** > + * > + * Copyright 2019 (C) Alistair Francis <alistair.francis@wdc.com> > + * Copyright 2021 (C) Bobby Eshleman <bobby.eshleman@gmail.com> > + * Copyright 2023 (C) Vates > + * > + */ > + > +#ifndef _ASM_RISCV_PROCESSOR_H > +#define _ASM_RISCV_PROCESSOR_H > + > +#ifndef __ASSEMBLY__ > + > +/* On stack VCPU state */ > +struct cpu_user_regs > +{ > + unsigned long zero; > + unsigned long ra; > + unsigned long sp; > + unsigned long gp; > + unsigned long tp; > + unsigned long t0; > + unsigned long t1; > + unsigned long t2; > + unsigned long s0; > + unsigned long s1; > + unsigned long a0; > + unsigned long a1; > + unsigned long a2; > + unsigned long a3; > + unsigned long a4; > + unsigned long a5; > + unsigned long a6; > + unsigned long a7; > + unsigned long s2; > + unsigned long s3; > + unsigned long s4; > + unsigned long s5; > + unsigned long s6; > + unsigned long s7; > + unsigned long s8; > + unsigned long s9; > + unsigned long s10; > + unsigned long s11; > + unsigned long t3; > + unsigned long t4; > + unsigned long t5; > + unsigned long t6; > + unsigned long sepc; > + unsigned long sstatus; > + /* pointer to previous stack_cpu_regs */ > + unsigned long pregs; > +}; > + > +static inline void wfi(void) > +{ > + __asm__ __volatile__ ("wfi"); > +} > + > +/* > + * panic() isn't available at the moment so an infinite loop will be > + * used temporarily. > + * TODO: change it to panic() > + */ > +static inline void die(void) > +{ > + for ( ;; ) > + wfi(); > +} > + > +#endif /* __ASSEMBLY__ */ > + > +#endif /* _ASM_RISCV_PROCESSOR_H */ > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/arch/riscv/riscv64/asm-offsets.c b/xen/arch/riscv/riscv64/asm-offsets.c > index e69de29bb2..d632b75c2a 100644 > --- a/xen/arch/riscv/riscv64/asm-offsets.c > +++ b/xen/arch/riscv/riscv64/asm-offsets.c > @@ -0,0 +1,53 @@ > +#define COMPILE_OFFSETS > + > +#include <asm/processor.h> > +#include <xen/types.h> > + > +#define DEFINE(_sym, _val) \ > + asm volatile ("\n.ascii\"==>#define " #_sym " %0 /* " #_val " */<==\"" \ > + : : "i" (_val) ) > +#define BLANK() \ > + asm volatile ( "\n.ascii\"==><==\"" : : ) > +#define OFFSET(_sym, _str, _mem) \ > + DEFINE(_sym, offsetof(_str, _mem)); > + > +void asm_offsets(void) > +{ > + BLANK(); > + DEFINE(CPU_USER_REGS_SIZE, sizeof(struct cpu_user_regs)); > + OFFSET(CPU_USER_REGS_ZERO, struct cpu_user_regs, zero); > + OFFSET(CPU_USER_REGS_RA, struct cpu_user_regs, ra); > + OFFSET(CPU_USER_REGS_SP, struct cpu_user_regs, sp); > + OFFSET(CPU_USER_REGS_GP, struct cpu_user_regs, gp); > + OFFSET(CPU_USER_REGS_TP, struct cpu_user_regs, tp); > + OFFSET(CPU_USER_REGS_T0, struct cpu_user_regs, t0); > + OFFSET(CPU_USER_REGS_T1, struct cpu_user_regs, t1); > + OFFSET(CPU_USER_REGS_T2, struct cpu_user_regs, t2); > + OFFSET(CPU_USER_REGS_S0, struct cpu_user_regs, s0); > + OFFSET(CPU_USER_REGS_S1, struct cpu_user_regs, s1); > + OFFSET(CPU_USER_REGS_A0, struct cpu_user_regs, a0); > + OFFSET(CPU_USER_REGS_A1, struct cpu_user_regs, a1); > + OFFSET(CPU_USER_REGS_A2, struct cpu_user_regs, a2); > + OFFSET(CPU_USER_REGS_A3, struct cpu_user_regs, a3); > + OFFSET(CPU_USER_REGS_A4, struct cpu_user_regs, a4); > + OFFSET(CPU_USER_REGS_A5, struct cpu_user_regs, a5); > + OFFSET(CPU_USER_REGS_A6, struct cpu_user_regs, a6); > + OFFSET(CPU_USER_REGS_A7, struct cpu_user_regs, a7); > + OFFSET(CPU_USER_REGS_S2, struct cpu_user_regs, s2); > + OFFSET(CPU_USER_REGS_S3, struct cpu_user_regs, s3); > + OFFSET(CPU_USER_REGS_S4, struct cpu_user_regs, s4); > + OFFSET(CPU_USER_REGS_S5, struct cpu_user_regs, s5); > + OFFSET(CPU_USER_REGS_S6, struct cpu_user_regs, s6); > + OFFSET(CPU_USER_REGS_S7, struct cpu_user_regs, s7); > + OFFSET(CPU_USER_REGS_S8, struct cpu_user_regs, s8); > + OFFSET(CPU_USER_REGS_S9, struct cpu_user_regs, s9); > + OFFSET(CPU_USER_REGS_S10, struct cpu_user_regs, s10); > + OFFSET(CPU_USER_REGS_S11, struct cpu_user_regs, s11); > + OFFSET(CPU_USER_REGS_T3, struct cpu_user_regs, t3); > + OFFSET(CPU_USER_REGS_T4, struct cpu_user_regs, t4); > + OFFSET(CPU_USER_REGS_T5, struct cpu_user_regs, t5); > + OFFSET(CPU_USER_REGS_T6, struct cpu_user_regs, t6); > + OFFSET(CPU_USER_REGS_SEPC, struct cpu_user_regs, sepc); > + OFFSET(CPU_USER_REGS_SSTATUS, struct cpu_user_regs, sstatus); > + OFFSET(CPU_USER_REGS_PREGS, struct cpu_user_regs, pregs); > +} > -- > 2.39.0 > >
diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/include/asm/processor.h new file mode 100644 index 0000000000..a71448e02e --- /dev/null +++ b/xen/arch/riscv/include/asm/processor.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: MIT */ +/****************************************************************************** + * + * Copyright 2019 (C) Alistair Francis <alistair.francis@wdc.com> + * Copyright 2021 (C) Bobby Eshleman <bobby.eshleman@gmail.com> + * Copyright 2023 (C) Vates + * + */ + +#ifndef _ASM_RISCV_PROCESSOR_H +#define _ASM_RISCV_PROCESSOR_H + +#ifndef __ASSEMBLY__ + +/* On stack VCPU state */ +struct cpu_user_regs +{ + unsigned long zero; + unsigned long ra; + unsigned long sp; + unsigned long gp; + unsigned long tp; + unsigned long t0; + unsigned long t1; + unsigned long t2; + unsigned long s0; + unsigned long s1; + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; + unsigned long a4; + unsigned long a5; + unsigned long a6; + unsigned long a7; + unsigned long s2; + unsigned long s3; + unsigned long s4; + unsigned long s5; + unsigned long s6; + unsigned long s7; + unsigned long s8; + unsigned long s9; + unsigned long s10; + unsigned long s11; + unsigned long t3; + unsigned long t4; + unsigned long t5; + unsigned long t6; + unsigned long sepc; + unsigned long sstatus; + /* pointer to previous stack_cpu_regs */ + unsigned long pregs; +}; + +static inline void wfi(void) +{ + __asm__ __volatile__ ("wfi"); +} + +/* + * panic() isn't available at the moment so an infinite loop will be + * used temporarily. + * TODO: change it to panic() + */ +static inline void die(void) +{ + for ( ;; ) + wfi(); +} + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_PROCESSOR_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/riscv/riscv64/asm-offsets.c b/xen/arch/riscv/riscv64/asm-offsets.c index e69de29bb2..d632b75c2a 100644 --- a/xen/arch/riscv/riscv64/asm-offsets.c +++ b/xen/arch/riscv/riscv64/asm-offsets.c @@ -0,0 +1,53 @@ +#define COMPILE_OFFSETS + +#include <asm/processor.h> +#include <xen/types.h> + +#define DEFINE(_sym, _val) \ + asm volatile ("\n.ascii\"==>#define " #_sym " %0 /* " #_val " */<==\"" \ + : : "i" (_val) ) +#define BLANK() \ + asm volatile ( "\n.ascii\"==><==\"" : : ) +#define OFFSET(_sym, _str, _mem) \ + DEFINE(_sym, offsetof(_str, _mem)); + +void asm_offsets(void) +{ + BLANK(); + DEFINE(CPU_USER_REGS_SIZE, sizeof(struct cpu_user_regs)); + OFFSET(CPU_USER_REGS_ZERO, struct cpu_user_regs, zero); + OFFSET(CPU_USER_REGS_RA, struct cpu_user_regs, ra); + OFFSET(CPU_USER_REGS_SP, struct cpu_user_regs, sp); + OFFSET(CPU_USER_REGS_GP, struct cpu_user_regs, gp); + OFFSET(CPU_USER_REGS_TP, struct cpu_user_regs, tp); + OFFSET(CPU_USER_REGS_T0, struct cpu_user_regs, t0); + OFFSET(CPU_USER_REGS_T1, struct cpu_user_regs, t1); + OFFSET(CPU_USER_REGS_T2, struct cpu_user_regs, t2); + OFFSET(CPU_USER_REGS_S0, struct cpu_user_regs, s0); + OFFSET(CPU_USER_REGS_S1, struct cpu_user_regs, s1); + OFFSET(CPU_USER_REGS_A0, struct cpu_user_regs, a0); + OFFSET(CPU_USER_REGS_A1, struct cpu_user_regs, a1); + OFFSET(CPU_USER_REGS_A2, struct cpu_user_regs, a2); + OFFSET(CPU_USER_REGS_A3, struct cpu_user_regs, a3); + OFFSET(CPU_USER_REGS_A4, struct cpu_user_regs, a4); + OFFSET(CPU_USER_REGS_A5, struct cpu_user_regs, a5); + OFFSET(CPU_USER_REGS_A6, struct cpu_user_regs, a6); + OFFSET(CPU_USER_REGS_A7, struct cpu_user_regs, a7); + OFFSET(CPU_USER_REGS_S2, struct cpu_user_regs, s2); + OFFSET(CPU_USER_REGS_S3, struct cpu_user_regs, s3); + OFFSET(CPU_USER_REGS_S4, struct cpu_user_regs, s4); + OFFSET(CPU_USER_REGS_S5, struct cpu_user_regs, s5); + OFFSET(CPU_USER_REGS_S6, struct cpu_user_regs, s6); + OFFSET(CPU_USER_REGS_S7, struct cpu_user_regs, s7); + OFFSET(CPU_USER_REGS_S8, struct cpu_user_regs, s8); + OFFSET(CPU_USER_REGS_S9, struct cpu_user_regs, s9); + OFFSET(CPU_USER_REGS_S10, struct cpu_user_regs, s10); + OFFSET(CPU_USER_REGS_S11, struct cpu_user_regs, s11); + OFFSET(CPU_USER_REGS_T3, struct cpu_user_regs, t3); + OFFSET(CPU_USER_REGS_T4, struct cpu_user_regs, t4); + OFFSET(CPU_USER_REGS_T5, struct cpu_user_regs, t5); + OFFSET(CPU_USER_REGS_T6, struct cpu_user_regs, t6); + OFFSET(CPU_USER_REGS_SEPC, struct cpu_user_regs, sepc); + OFFSET(CPU_USER_REGS_SSTATUS, struct cpu_user_regs, sstatus); + OFFSET(CPU_USER_REGS_PREGS, struct cpu_user_regs, pregs); +}
The patch introduces a set of registers which should be saved to and restored from a stack after an exception occurs and a set of defines which will be used during exception context saving/restoring. Originally <asm/processor.h> header was introduced in the patch series from Bobby so partially it was re-used and the following changes were done: - Move all RISCV_CPU_USER_REGS_* to asm/asm-offsets.c - Remove RISCV_CPU_USER_REGS_OFFSET & RISCV_CPU_USER_REGS_SIZE as there is no sense in them after RISCV_CPU_USER_REGS_* were moved to asm/asm-offsets.c - Remove RISCV_PCPUINFO_* as they aren't needed for current status of the RISC-V port - register_t renamed to unsigned long - rename wait_for_interrupt to wfi Signed-off-by: Bobby Eshleman <bobby.eshleman@gmail.com> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> --- Changes in V3: - update code style for die() function --- Changes in V2: - All the changes were added to the commit message. - temporarily was added function die() to stop exectution it will be removed after panic() will be available. --- xen/arch/riscv/include/asm/processor.h | 83 ++++++++++++++++++++++++++ xen/arch/riscv/riscv64/asm-offsets.c | 53 ++++++++++++++++ 2 files changed, 136 insertions(+) create mode 100644 xen/arch/riscv/include/asm/processor.h