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[46.204.109.85]) by smtp.gmail.com with ESMTPSA id h10-20020a5d4fca000000b002c3e94cb757sm5269743wrw.117.2023.02.07.06.47.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Feb 2023 06:47:04 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4a3b7ca3-a6f6-11ed-933c-83870f6b2ba8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CM5HAZAjC5AS1XK7mKrfXtpw4DHmLtXflVKppyEPcdo=; b=QBriLcpZb17+mIDzi2hjXl/GfUukjGfTQRZexvrZ+QPKD1zSlUt5+GASQzCrg8Gy8A P8bgxeSlxuW/ydZTZI7mRfFUHCaz6RqcaXmKkXk1k8dcN+zDwUwH+qnZsXfwsKaL7rfV XwXL/dSjYDxq6N72X/6Y+WDdYlpSDwyMKdzE2IUazeOWiGSeRtlTkm9w16LCEOMckSMi 1Y42XMiG9rCudzursKW6xmFLU7Z5hCNqBMQDk2hbwN4r/GbYnxzLYifj1jSaQQzhdYSE tXSyi192ftfYr1P0P9NI1zfcEmpQAvlb9zMpnAWYhtenPgJKEgJh09snizFHNY7rFFUF 4hDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CM5HAZAjC5AS1XK7mKrfXtpw4DHmLtXflVKppyEPcdo=; b=D/aeDHjw27MwWf1yvN6pTXLUVNpIxbtTfLVDCqsLHoIWIWydKCd8N2r3McrRoYXVR+ g1hd8VpKTOxbZ0IWRATbsCOnaCLraCqCYOeHhhr8sirH2FIdgNfCWz1RGBYQ6NO1zrRl 5PoJLtEListljkHTLsrsSBkS/dCdjd9QxrTLt71TlWYhgQPchwKWXOvhq8ce3Ofitw9e 5/W2iKEFwxFrY1ucFDA1nrZZ/nTJU2FyaN+J+GXLiBpotpKyCB79IuAMvRfDB4+tSuuS BTqDk9uXj6z0Zh/8U2+MngCv437MoXkr/uxtZPzKVd8ajXHOu7rgogW1YR/qo/TZMsyg o8vA== X-Gm-Message-State: AO0yUKU9zeAAD74Zy+UoY3MS3TXOr0eZqWzqIQSjPRbmpWVGlXU6DigA xp1J+t5ilVbgzSBK4MGlKP9EZQRI6yI= X-Google-Smtp-Source: AK7set9ECa3KSNKJ9bKD3YYek4ecROKFNbQm3F0y6p2soM6Yv1NRvKI0Jzh3WUrYcgqWkTpTMDqIkQ== X-Received: by 2002:adf:f80c:0:b0:2c3:cdcd:f0b3 with SMTP id s12-20020adff80c000000b002c3cdcdf0b3mr2739661wrp.9.1675781225280; Tue, 07 Feb 2023 06:47:05 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Jan Beulich , Julien Grall , Andrew Cooper , Stefano Stabellini , Gianluca Guida , Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis , Bobby Eshleman Subject: [PATCH v3 07/14] xen/riscv: introduce exception context Date: Tue, 7 Feb 2023 16:46:42 +0200 Message-Id: <5aa05592497ba9c4d207185d81981442d43ba676.1675780434.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: References: MIME-Version: 1.0 The patch introduces a set of registers which should be saved to and restored from a stack after an exception occurs and a set of defines which will be used during exception context saving/restoring. Originally header was introduced in the patch series from Bobby so partially it was re-used and the following changes were done: - Move all RISCV_CPU_USER_REGS_* to asm/asm-offsets.c - Remove RISCV_CPU_USER_REGS_OFFSET & RISCV_CPU_USER_REGS_SIZE as there is no sense in them after RISCV_CPU_USER_REGS_* were moved to asm/asm-offsets.c - Remove RISCV_PCPUINFO_* as they aren't needed for current status of the RISC-V port - register_t renamed to unsigned long - rename wait_for_interrupt to wfi Signed-off-by: Bobby Eshleman Signed-off-by: Oleksii Kurochko Reviewed-by: Alistair Francis --- Changes in V3: - update code style for die() function --- Changes in V2: - All the changes were added to the commit message. - temporarily was added function die() to stop exectution it will be removed after panic() will be available. --- xen/arch/riscv/include/asm/processor.h | 83 ++++++++++++++++++++++++++ xen/arch/riscv/riscv64/asm-offsets.c | 53 ++++++++++++++++ 2 files changed, 136 insertions(+) create mode 100644 xen/arch/riscv/include/asm/processor.h diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/include/asm/processor.h new file mode 100644 index 0000000000..a71448e02e --- /dev/null +++ b/xen/arch/riscv/include/asm/processor.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: MIT */ +/****************************************************************************** + * + * Copyright 2019 (C) Alistair Francis + * Copyright 2021 (C) Bobby Eshleman + * Copyright 2023 (C) Vates + * + */ + +#ifndef _ASM_RISCV_PROCESSOR_H +#define _ASM_RISCV_PROCESSOR_H + +#ifndef __ASSEMBLY__ + +/* On stack VCPU state */ +struct cpu_user_regs +{ + unsigned long zero; + unsigned long ra; + unsigned long sp; + unsigned long gp; + unsigned long tp; + unsigned long t0; + unsigned long t1; + unsigned long t2; + unsigned long s0; + unsigned long s1; + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; + unsigned long a4; + unsigned long a5; + unsigned long a6; + unsigned long a7; + unsigned long s2; + unsigned long s3; + unsigned long s4; + unsigned long s5; + unsigned long s6; + unsigned long s7; + unsigned long s8; + unsigned long s9; + unsigned long s10; + unsigned long s11; + unsigned long t3; + unsigned long t4; + unsigned long t5; + unsigned long t6; + unsigned long sepc; + unsigned long sstatus; + /* pointer to previous stack_cpu_regs */ + unsigned long pregs; +}; + +static inline void wfi(void) +{ + __asm__ __volatile__ ("wfi"); +} + +/* + * panic() isn't available at the moment so an infinite loop will be + * used temporarily. + * TODO: change it to panic() + */ +static inline void die(void) +{ + for ( ;; ) + wfi(); +} + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_PROCESSOR_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/riscv/riscv64/asm-offsets.c b/xen/arch/riscv/riscv64/asm-offsets.c index e69de29bb2..d632b75c2a 100644 --- a/xen/arch/riscv/riscv64/asm-offsets.c +++ b/xen/arch/riscv/riscv64/asm-offsets.c @@ -0,0 +1,53 @@ +#define COMPILE_OFFSETS + +#include +#include + +#define DEFINE(_sym, _val) \ + asm volatile ("\n.ascii\"==>#define " #_sym " %0 /* " #_val " */<==\"" \ + : : "i" (_val) ) +#define BLANK() \ + asm volatile ( "\n.ascii\"==><==\"" : : ) +#define OFFSET(_sym, _str, _mem) \ + DEFINE(_sym, offsetof(_str, _mem)); + +void asm_offsets(void) +{ + BLANK(); + DEFINE(CPU_USER_REGS_SIZE, sizeof(struct cpu_user_regs)); + OFFSET(CPU_USER_REGS_ZERO, struct cpu_user_regs, zero); + OFFSET(CPU_USER_REGS_RA, struct cpu_user_regs, ra); + OFFSET(CPU_USER_REGS_SP, struct cpu_user_regs, sp); + OFFSET(CPU_USER_REGS_GP, struct cpu_user_regs, gp); + OFFSET(CPU_USER_REGS_TP, struct cpu_user_regs, tp); + OFFSET(CPU_USER_REGS_T0, struct cpu_user_regs, t0); + OFFSET(CPU_USER_REGS_T1, struct cpu_user_regs, t1); + OFFSET(CPU_USER_REGS_T2, struct cpu_user_regs, t2); + OFFSET(CPU_USER_REGS_S0, struct cpu_user_regs, s0); + OFFSET(CPU_USER_REGS_S1, struct cpu_user_regs, s1); + OFFSET(CPU_USER_REGS_A0, struct cpu_user_regs, a0); + OFFSET(CPU_USER_REGS_A1, struct cpu_user_regs, a1); + OFFSET(CPU_USER_REGS_A2, struct cpu_user_regs, a2); + OFFSET(CPU_USER_REGS_A3, struct cpu_user_regs, a3); + OFFSET(CPU_USER_REGS_A4, struct cpu_user_regs, a4); + OFFSET(CPU_USER_REGS_A5, struct cpu_user_regs, a5); + OFFSET(CPU_USER_REGS_A6, struct cpu_user_regs, a6); + OFFSET(CPU_USER_REGS_A7, struct cpu_user_regs, a7); + OFFSET(CPU_USER_REGS_S2, struct cpu_user_regs, s2); + OFFSET(CPU_USER_REGS_S3, struct cpu_user_regs, s3); + OFFSET(CPU_USER_REGS_S4, struct cpu_user_regs, s4); + OFFSET(CPU_USER_REGS_S5, struct cpu_user_regs, s5); + OFFSET(CPU_USER_REGS_S6, struct cpu_user_regs, s6); + OFFSET(CPU_USER_REGS_S7, struct cpu_user_regs, s7); + OFFSET(CPU_USER_REGS_S8, struct cpu_user_regs, s8); + OFFSET(CPU_USER_REGS_S9, struct cpu_user_regs, s9); + OFFSET(CPU_USER_REGS_S10, struct cpu_user_regs, s10); + OFFSET(CPU_USER_REGS_S11, struct cpu_user_regs, s11); + OFFSET(CPU_USER_REGS_T3, struct cpu_user_regs, t3); + OFFSET(CPU_USER_REGS_T4, struct cpu_user_regs, t4); + OFFSET(CPU_USER_REGS_T5, struct cpu_user_regs, t5); + OFFSET(CPU_USER_REGS_T6, struct cpu_user_regs, t6); + OFFSET(CPU_USER_REGS_SEPC, struct cpu_user_regs, sepc); + OFFSET(CPU_USER_REGS_SSTATUS, struct cpu_user_regs, sstatus); + OFFSET(CPU_USER_REGS_PREGS, struct cpu_user_regs, pregs); +}