| Message ID | 621e8ef8c6a721927ecade5bb41cdc85df386bbf.1674226563.git.oleksii.kurochko@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISCV basic exception handling implementation | expand |
On 20/01/2023 2:59 pm, Oleksii Kurochko wrote:
> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
There's some stuff in here which is not RISCV-specific. We really want
to dedup with the other architectures and move into common.
~Andrew
On Sat, Jan 21, 2023 at 1:00 AM Oleksii Kurochko <oleksii.kurochko@gmail.com> wrote: > > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > xen/arch/riscv/include/asm/asm.h | 54 ++++++++++++++++++++++++++++++++ > 1 file changed, 54 insertions(+) > create mode 100644 xen/arch/riscv/include/asm/asm.h > > diff --git a/xen/arch/riscv/include/asm/asm.h b/xen/arch/riscv/include/asm/asm.h > new file mode 100644 > index 0000000000..6d426ecea7 > --- /dev/null > +++ b/xen/arch/riscv/include/asm/asm.h > @@ -0,0 +1,54 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only) */ > +/* > + * Copyright (C) 2015 Regents of the University of California > + */ > + > +#ifndef _ASM_RISCV_ASM_H > +#define _ASM_RISCV_ASM_H > + > +#ifdef __ASSEMBLY__ > +#define __ASM_STR(x) x > +#else > +#define __ASM_STR(x) #x > +#endif > + > +#if __riscv_xlen == 64 > +#define __REG_SEL(a, b) __ASM_STR(a) > +#elif __riscv_xlen == 32 > +#define __REG_SEL(a, b) __ASM_STR(b) > +#else > +#error "Unexpected __riscv_xlen" > +#endif > + > +#define REG_L __REG_SEL(ld, lw) > +#define REG_S __REG_SEL(sd, sw) > + > +#if __SIZEOF_POINTER__ == 8 > +#ifdef __ASSEMBLY__ > +#define RISCV_PTR .dword > +#else > +#define RISCV_PTR ".dword" > +#endif > +#elif __SIZEOF_POINTER__ == 4 > +#ifdef __ASSEMBLY__ > +#define RISCV_PTR .word > +#else > +#define RISCV_PTR ".word" > +#endif > +#else > +#error "Unexpected __SIZEOF_POINTER__" > +#endif > + > +#if (__SIZEOF_INT__ == 4) > +#define RISCV_INT __ASM_STR(.word) > +#else > +#error "Unexpected __SIZEOF_INT__" > +#endif > + > +#if (__SIZEOF_SHORT__ == 2) > +#define RISCV_SHORT __ASM_STR(.half) > +#else > +#error "Unexpected __SIZEOF_SHORT__" > +#endif > + > +#endif /* _ASM_RISCV_ASM_H */ > -- > 2.39.0 > >
On 20.01.2023 16:31, Andrew Cooper wrote: > On 20/01/2023 2:59 pm, Oleksii Kurochko wrote: >> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> > > There's some stuff in here which is not RISCV-specific. We really want > to dedup with the other architectures and move into common. I have to admit that I'm not fully convinced in this case: What an arch may or may not need in support of its assembly code may heavily vary. It would need to be very generic thing which could be moved out. Then again xen/asm.h feels like slightly odd a name with, as kind of already implied above, assembly code being at times very specific to an architecture (including e.g. formatting constraints or whether labels are to be followed by colons). Jan
On 23/01/2023 11:00 am, Jan Beulich wrote: > On 20.01.2023 16:31, Andrew Cooper wrote: >> On 20/01/2023 2:59 pm, Oleksii Kurochko wrote: >>> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> >> There's some stuff in here which is not RISCV-specific. We really want >> to dedup with the other architectures and move into common. > I have to admit that I'm not fully convinced in this case: What an arch > may or may not need in support of its assembly code may heavily vary. It > would need to be very generic thing which could be moved out. Then again > xen/asm.h feels like slightly odd a name with, as kind of already implied > above, assembly code being at times very specific to an architecture > (including e.g. formatting constraints or whether labels are to be > followed by colons). Half of this header file is re-inventing generic concepts that we already spell differently in the Xen codebase. It is the difference between bolting something on the side, and integrating the code properly. ~Andrew
diff --git a/xen/arch/riscv/include/asm/asm.h b/xen/arch/riscv/include/asm/asm.h new file mode 100644 index 0000000000..6d426ecea7 --- /dev/null +++ b/xen/arch/riscv/include/asm/asm.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: (GPL-2.0-only) */ +/* + * Copyright (C) 2015 Regents of the University of California + */ + +#ifndef _ASM_RISCV_ASM_H +#define _ASM_RISCV_ASM_H + +#ifdef __ASSEMBLY__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +#if __riscv_xlen == 64 +#define __REG_SEL(a, b) __ASM_STR(a) +#elif __riscv_xlen == 32 +#define __REG_SEL(a, b) __ASM_STR(b) +#else +#error "Unexpected __riscv_xlen" +#endif + +#define REG_L __REG_SEL(ld, lw) +#define REG_S __REG_SEL(sd, sw) + +#if __SIZEOF_POINTER__ == 8 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .dword +#else +#define RISCV_PTR ".dword" +#endif +#elif __SIZEOF_POINTER__ == 4 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .word +#else +#define RISCV_PTR ".word" +#endif +#else +#error "Unexpected __SIZEOF_POINTER__" +#endif + +#if (__SIZEOF_INT__ == 4) +#define RISCV_INT __ASM_STR(.word) +#else +#error "Unexpected __SIZEOF_INT__" +#endif + +#if (__SIZEOF_SHORT__ == 2) +#define RISCV_SHORT __ASM_STR(.half) +#else +#error "Unexpected __SIZEOF_SHORT__" +#endif + +#endif /* _ASM_RISCV_ASM_H */
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> --- xen/arch/riscv/include/asm/asm.h | 54 ++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 xen/arch/riscv/include/asm/asm.h