From patchwork Thu Aug 3 10:22:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13339693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99E52C001DF for ; Thu, 3 Aug 2023 10:27:32 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.576218.902128 (Exim 4.92) (envelope-from ) id 1qRVYC-00016W-1c; Thu, 03 Aug 2023 10:27:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 576218.902128; Thu, 03 Aug 2023 10:27:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qRVYB-00016L-V2; Thu, 03 Aug 2023 10:27:23 +0000 Received: by outflank-mailman (input) for mailman id 576218; Thu, 03 Aug 2023 10:27:23 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qRVYB-0000aV-0i for xen-devel@lists.xenproject.org; Thu, 03 Aug 2023 10:27:23 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 54644258-31e8-11ee-8613-37d641c3527e; Thu, 03 Aug 2023 12:27:21 +0200 (CEST) Received: from beta.station (net-188-218-251-179.cust.vodafonedsl.it [188.218.251.179]) by support.bugseng.com (Postfix) with ESMTPSA id BD84F4EE0737; Thu, 3 Aug 2023 12:27:20 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 54644258-31e8-11ee-8613-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Paul Durrant , Wei Liu , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Simone Ballarin Subject: [XEN PATCH 10/13] x86/viridian: address violations of MISRA C:2012 Rule 7.3 Date: Thu, 3 Aug 2023 12:22:25 +0200 Message-Id: <63f0d6385f302517244604af5536ffebd74ba589.1691053438.git.simone.ballarin@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contain violations of MISRA C:2012 Rule 7.3 whose headline states: "The lowercase character 'l' shall not be used in a literal suffix". Use the "L" suffix instead of the "l" suffix, to avoid potential ambiguity. If the "u" suffix is used near "L", use the "U" suffix instead, for consistency. The changes in this patch are mechanical. Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini Reviewed-by: Paul Durrant --- xen/arch/x86/hvm/viridian/synic.c | 2 +- xen/arch/x86/hvm/viridian/time.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/hvm/viridian/synic.c b/xen/arch/x86/hvm/viridian/synic.c index 83d7addfc3..8cf600cec6 100644 --- a/xen/arch/x86/hvm/viridian/synic.c +++ b/xen/arch/x86/hvm/viridian/synic.c @@ -233,7 +233,7 @@ int viridian_synic_rdmsr(const struct vcpu *v, uint32_t idx, uint64_t *val) * should be set to. Assume everything but the bottom bit * should be zero. */ - *val = 1ul; + *val = 1UL; break; case HV_X64_MSR_SIEFP: diff --git a/xen/arch/x86/hvm/viridian/time.c b/xen/arch/x86/hvm/viridian/time.c index a3ea3fa067..137577384f 100644 --- a/xen/arch/x86/hvm/viridian/time.c +++ b/xen/arch/x86/hvm/viridian/time.c @@ -66,7 +66,7 @@ static void update_reference_tsc(const struct domain *d, bool initialize) * The offset value is calculated on restore after migration and * ensures that Windows will not see a large jump in ReferenceTime. */ - p->tsc_scale = ((10000ul << 32) / d->arch.tsc_khz) << 32; + p->tsc_scale = ((10000UL << 32) / d->arch.tsc_khz) << 32; p->tsc_offset = trc->off; smp_wmb(); @@ -79,7 +79,7 @@ static uint64_t trc_val(const struct domain *d, int64_t offset) uint64_t tsc, scale; tsc = hvm_get_guest_tsc(pt_global_vcpu_target(d)); - scale = ((10000ul << 32) / d->arch.tsc_khz) << 32; + scale = ((10000UL << 32) / d->arch.tsc_khz) << 32; return hv_scale_tsc(tsc, scale, offset); } @@ -201,7 +201,7 @@ static void start_stimer(struct viridian_stimer *vs) ASSERT(expiration - now > 0); vs->expiration = expiration; - timeout = (expiration - now) * 100ull; + timeout = (expiration - now) * 100ULL; vs->started = true; clear_bit(stimerx, &vv->stimer_pending); @@ -413,14 +413,14 @@ int viridian_time_rdmsr(const struct vcpu *v, uint32_t idx, uint64_t *val) if ( viridian_feature_mask(d) & HVMPV_no_freq ) return X86EMUL_EXCEPTION; - *val = (uint64_t)d->arch.tsc_khz * 1000ull; + *val = (uint64_t)d->arch.tsc_khz * 1000ULL; break; case HV_X64_MSR_APIC_FREQUENCY: if ( viridian_feature_mask(d) & HVMPV_no_freq ) return X86EMUL_EXCEPTION; - *val = 1000000000ull / APIC_BUS_CYCLE_NS; + *val = 1000000000ULL / APIC_BUS_CYCLE_NS; break; case HV_X64_MSR_REFERENCE_TSC: