| Message ID | 6c2473a29d60460bf69382fd1e983752634b6992.1690368810.git.simone.ballarin@bugseng.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | xen: address violations of MISRA C:2012 Rule 7.2 | expand |
On 26/07/2023 13:03, Simone Ballarin wrote: > From: Gianluca Luparini <gianluca.luparini@bugseng.com> > > The xen sources contains violations of MISRA C:2012 Rule 7.2 whose > headline states: > "A 'u' or 'U' suffix shall be applied to all integer constants > that are represented in an unsigned type". > > Add the 'U' suffix to integers literals with unsigned type. > > For the sake of uniformity, the following changes are made: > - add the 'U' suffix to macros near > 'CPU_BASED_ACTIVATE_SECONDARY_CONTROLS' and > 'SECONDARY_EXEC_NOTIFY_VM_EXITING' macros in 'vmcs.h' > - add the 'U' suffix to macros near 'INTR_INFO_VALID_MASK' > macro in 'vmx.h' > > Signed-off-by: Gianluca Luparini <gianluca.luparini@bugseng.com> > Signed-off-by: Simone Ballarin <simone.ballarin@bugseng.com> > Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> > Reviewed-by: Jan Beulich <jbeulich@suse.com> > --- > Changes in v4: > - change commit headline > > Changes in v3: > - change 'Signed-off-by' ordering > - change commit message > - remove unnecessary changes in 'vvmx.c' > - add 'uint32_t' casts in 'vvmx.c' > - add missing 'U' in 'vmcs.h' macros > - change macro to '(1u << 31)' in 'vmx.h' > - remove unnecessary changes to 'vmx.h' > > Changes in v2: > - minor change to commit title > - change commit message > - remove unnecessary changes in 'vpmu_intel.c' and 'vmx.h' > - add 'ULL' suffix in 'vpmu_intel.c' > - add zero-padding to constants in 'vmx.h' > - add missing 'U' in 'vmx.h' > --- > xen/arch/x86/cpu/vpmu_intel.c | 2 +- > xen/arch/x86/hvm/vmx/vmcs.c | 6 +- > xen/arch/x86/hvm/vmx/vvmx.c | 8 +-- > xen/arch/x86/include/asm/hvm/vmx/vmcs.h | 84 ++++++++++++------------- > xen/arch/x86/include/asm/hvm/vmx/vmx.h | 16 ++--- > 5 files changed, 58 insertions(+), 58 deletions(-) > > diff --git a/xen/arch/x86/cpu/vpmu_intel.c > b/xen/arch/x86/cpu/vpmu_intel.c > index fa5b40c65c..6330c89b47 100644 > --- a/xen/arch/x86/cpu/vpmu_intel.c > +++ b/xen/arch/x86/cpu/vpmu_intel.c > @@ -945,7 +945,7 @@ const struct arch_vpmu_ops *__init > core2_vpmu_init(void) > fixed_counters_mask = ~((1ull << core2_get_bitwidth_fix_count()) - > 1); > global_ctrl_mask = ~((((1ULL << fixed_pmc_cnt) - 1) << 32) | > ((1ULL << arch_pmc_cnt) - 1)); > - global_ovf_ctrl_mask = ~(0xC000000000000000 | > + global_ovf_ctrl_mask = ~(0xC000000000000000ULL | > (((1ULL << fixed_pmc_cnt) - 1) << 32) | > ((1ULL << arch_pmc_cnt) - 1)); > if ( version > 2 ) > diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c > index 13719cc923..6cefb88aec 100644 > --- a/xen/arch/x86/hvm/vmx/vmcs.c > +++ b/xen/arch/x86/hvm/vmx/vmcs.c > @@ -911,7 +911,7 @@ void vmx_clear_msr_intercept(struct vcpu *v, > unsigned int msr, > if ( type & VMX_MSR_W ) > clear_bit(msr, msr_bitmap->write_low); > } > - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) > + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) > { > msr &= 0x1fff; > if ( type & VMX_MSR_R ) > @@ -939,7 +939,7 @@ void vmx_set_msr_intercept(struct vcpu *v, unsigned > int msr, > if ( type & VMX_MSR_W ) > set_bit(msr, msr_bitmap->write_low); > } > - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) > + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) > { > msr &= 0x1fff; > if ( type & VMX_MSR_R ) > @@ -957,7 +957,7 @@ bool vmx_msr_is_intercepted(struct vmx_msr_bitmap > *msr_bitmap, > if ( msr <= 0x1fff ) > return test_bit(msr, is_write ? msr_bitmap->write_low > : msr_bitmap->read_low); > - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) > + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) > return test_bit(msr & 0x1fff, is_write ? > msr_bitmap->write_high > : > msr_bitmap->read_high); > else > diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c > index 16b0ef82b6..b7be424afb 100644 > --- a/xen/arch/x86/hvm/vmx/vvmx.c > +++ b/xen/arch/x86/hvm/vmx/vvmx.c > @@ -263,7 +263,7 @@ uint64_t get_vvmcs_virtual(void *vvmcs, uint32_t > vmcs_encoding) > res >>= 32; > break; > case VVMCS_WIDTH_32: > - res &= 0xffffffff; > + res = (uint32_t)res; > break; > case VVMCS_WIDTH_NATURAL: > default: > @@ -315,14 +315,14 @@ void set_vvmcs_virtual(void *vvmcs, uint32_t > vmcs_encoding, uint64_t val) > case VVMCS_WIDTH_64: > if ( enc.access_type ) > { > - res &= 0xffffffff; > + res = (uint32_t)res; > res |= val << 32; > } > else > res = val; > break; > case VVMCS_WIDTH_32: > - res = val & 0xffffffff; > + res = (uint32_t)val; > break; > case VVMCS_WIDTH_NATURAL: > default: > @@ -2306,7 +2306,7 @@ int nvmx_msr_read_intercept(unsigned int msr, > u64 *msr_content) > break; > case MSR_IA32_VMX_CR0_FIXED1: > /* allow 0-settings for all bits */ > - data = 0xffffffff; > + data = 0xffffffffU; > break; > case MSR_IA32_VMX_CR4_FIXED0: > /* VMXE bit must be 1 in VMX operation */ > diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h > b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h > index d07fcb2bc9..e056643993 100644 > --- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h > +++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h > @@ -187,27 +187,27 @@ bool_t __must_check vmx_vmcs_try_enter(struct > vcpu *v); > void vmx_vmcs_exit(struct vcpu *v); > void vmx_vmcs_reload(struct vcpu *v); > > -#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 > -#define CPU_BASED_USE_TSC_OFFSETING 0x00000008 > -#define CPU_BASED_HLT_EXITING 0x00000080 > -#define CPU_BASED_INVLPG_EXITING 0x00000200 > -#define CPU_BASED_MWAIT_EXITING 0x00000400 > -#define CPU_BASED_RDPMC_EXITING 0x00000800 > -#define CPU_BASED_RDTSC_EXITING 0x00001000 > -#define CPU_BASED_CR3_LOAD_EXITING 0x00008000 > -#define CPU_BASED_CR3_STORE_EXITING 0x00010000 > -#define CPU_BASED_CR8_LOAD_EXITING 0x00080000 > -#define CPU_BASED_CR8_STORE_EXITING 0x00100000 > -#define CPU_BASED_TPR_SHADOW 0x00200000 > -#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 > -#define CPU_BASED_MOV_DR_EXITING 0x00800000 > -#define CPU_BASED_UNCOND_IO_EXITING 0x01000000 > -#define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000 > -#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 > -#define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000 > -#define CPU_BASED_MONITOR_EXITING 0x20000000 > -#define CPU_BASED_PAUSE_EXITING 0x40000000 > -#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 > +#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004U > +#define CPU_BASED_USE_TSC_OFFSETING 0x00000008U > +#define CPU_BASED_HLT_EXITING 0x00000080U > +#define CPU_BASED_INVLPG_EXITING 0x00000200U > +#define CPU_BASED_MWAIT_EXITING 0x00000400U > +#define CPU_BASED_RDPMC_EXITING 0x00000800U > +#define CPU_BASED_RDTSC_EXITING 0x00001000U > +#define CPU_BASED_CR3_LOAD_EXITING 0x00008000U > +#define CPU_BASED_CR3_STORE_EXITING 0x00010000U > +#define CPU_BASED_CR8_LOAD_EXITING 0x00080000U > +#define CPU_BASED_CR8_STORE_EXITING 0x00100000U > +#define CPU_BASED_TPR_SHADOW 0x00200000U > +#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000U > +#define CPU_BASED_MOV_DR_EXITING 0x00800000U > +#define CPU_BASED_UNCOND_IO_EXITING 0x01000000U > +#define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000U > +#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000U > +#define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000U > +#define CPU_BASED_MONITOR_EXITING 0x20000000U > +#define CPU_BASED_PAUSE_EXITING 0x40000000U > +#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000U > extern u32 vmx_cpu_based_exec_control; > > #define PIN_BASED_EXT_INTR_MASK 0x00000001 > @@ -238,26 +238,26 @@ extern u32 vmx_vmexit_control; > #define VM_ENTRY_LOAD_BNDCFGS 0x00010000 > extern u32 vmx_vmentry_control; > > -#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 > -#define SECONDARY_EXEC_ENABLE_EPT 0x00000002 > -#define SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING 0x00000004 > -#define SECONDARY_EXEC_ENABLE_RDTSCP 0x00000008 > -#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 > -#define SECONDARY_EXEC_ENABLE_VPID 0x00000020 > -#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 > -#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 > -#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 > -#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 > -#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 > -#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 > -#define SECONDARY_EXEC_ENABLE_VM_FUNCTIONS 0x00002000 > -#define SECONDARY_EXEC_ENABLE_VMCS_SHADOWING 0x00004000 > -#define SECONDARY_EXEC_ENABLE_PML 0x00020000 > -#define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000 > -#define SECONDARY_EXEC_XSAVES 0x00100000 > -#define SECONDARY_EXEC_TSC_SCALING 0x02000000 > -#define SECONDARY_EXEC_BUS_LOCK_DETECTION 0x40000000 > -#define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000 > +#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001U > +#define SECONDARY_EXEC_ENABLE_EPT 0x00000002U > +#define SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING 0x00000004U > +#define SECONDARY_EXEC_ENABLE_RDTSCP 0x00000008U > +#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010U > +#define SECONDARY_EXEC_ENABLE_VPID 0x00000020U > +#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040U > +#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080U > +#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100U > +#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200U > +#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400U > +#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000U > +#define SECONDARY_EXEC_ENABLE_VM_FUNCTIONS 0x00002000U > +#define SECONDARY_EXEC_ENABLE_VMCS_SHADOWING 0x00004000U > +#define SECONDARY_EXEC_ENABLE_PML 0x00020000U > +#define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000U > +#define SECONDARY_EXEC_XSAVES 0x00100000U > +#define SECONDARY_EXEC_TSC_SCALING 0x02000000U > +#define SECONDARY_EXEC_BUS_LOCK_DETECTION 0x40000000U > +#define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000U > extern u32 vmx_secondary_exec_control; > > #define VMX_EPT_EXEC_ONLY_SUPPORTED 0x00000001 > @@ -346,7 +346,7 @@ extern u64 vmx_ept_vpid_cap; > #define cpu_has_vmx_notify_vm_exiting \ > (vmx_secondary_exec_control & SECONDARY_EXEC_NOTIFY_VM_EXITING) > > -#define VMCS_RID_TYPE_MASK 0x80000000 > +#define VMCS_RID_TYPE_MASK 0x80000000U > > /* GUEST_INTERRUPTIBILITY_INFO flags. */ > #define VMX_INTR_SHADOW_STI 0x00000001 > diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h > b/xen/arch/x86/include/asm/hvm/vmx/vmx.h > index c84acc221d..d4b335a2bc 100644 > --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h > +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h > @@ -137,7 +137,7 @@ static inline void pi_clear_sn(struct pi_desc > *pi_desc) > /* > * Exit Reasons > */ > -#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000 > +#define VMX_EXIT_REASONS_FAILED_VMENTRY (1u << 31) > #define VMX_EXIT_REASONS_BUS_LOCK (1u << 26) > > #define EXIT_REASON_EXCEPTION_NMI 0 > @@ -209,12 +209,12 @@ static inline void pi_clear_sn(struct pi_desc > *pi_desc) > * Note INTR_INFO_NMI_UNBLOCKED_BY_IRET is also used with Exit > Qualification > * field for EPT violations, PML full and SPP-related event vmexits. > */ > -#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ > -#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ > -#define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ > -#define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x1000 /* 12 */ > -#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ > -#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000 > +#define INTR_INFO_VECTOR_MASK 0x000000ffU /* 7:0 */ > +#define INTR_INFO_INTR_TYPE_MASK 0x00000700U /* 10:8 */ > +#define INTR_INFO_DELIVER_CODE_MASK 0x00000800U /* 11 */ > +#define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x00001000U /* 12 */ > +#define INTR_INFO_VALID_MASK 0x80000000U /* 31 */ > +#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000U > > /* > * Exit Qualifications for NOTIFY VM EXIT > @@ -607,7 +607,7 @@ static inline void vmx_pi_hooks_assign(struct > domain *d) {} > static inline void vmx_pi_hooks_deassign(struct domain *d) {} > #endif > > -#define APIC_INVALID_DEST 0xffffffff > +#define APIC_INVALID_DEST 0xffffffffU > > /* EPT violation qualifications definitions */ > typedef union ept_qual { I checked that this patch still applies cleanly on the current staging branch. Can this get an ack from the VT-X maintainer(s)?
On Thu, 24 Aug 2023, Nicola Vetrini wrote: > On 26/07/2023 13:03, Simone Ballarin wrote: > > From: Gianluca Luparini <gianluca.luparini@bugseng.com> > > > > The xen sources contains violations of MISRA C:2012 Rule 7.2 whose > > headline states: > > "A 'u' or 'U' suffix shall be applied to all integer constants > > that are represented in an unsigned type". > > > > Add the 'U' suffix to integers literals with unsigned type. > > > > For the sake of uniformity, the following changes are made: > > - add the 'U' suffix to macros near > > 'CPU_BASED_ACTIVATE_SECONDARY_CONTROLS' and > > 'SECONDARY_EXEC_NOTIFY_VM_EXITING' macros in 'vmcs.h' > > - add the 'U' suffix to macros near 'INTR_INFO_VALID_MASK' > > macro in 'vmx.h' > > > > Signed-off-by: Gianluca Luparini <gianluca.luparini@bugseng.com> > > Signed-off-by: Simone Ballarin <simone.ballarin@bugseng.com> > > Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> > > Reviewed-by: Jan Beulich <jbeulich@suse.com> > > --- > > Changes in v4: > > - change commit headline > > > > Changes in v3: > > - change 'Signed-off-by' ordering > > - change commit message > > - remove unnecessary changes in 'vvmx.c' > > - add 'uint32_t' casts in 'vvmx.c' > > - add missing 'U' in 'vmcs.h' macros > > - change macro to '(1u << 31)' in 'vmx.h' > > - remove unnecessary changes to 'vmx.h' > > > > Changes in v2: > > - minor change to commit title > > - change commit message > > - remove unnecessary changes in 'vpmu_intel.c' and 'vmx.h' > > - add 'ULL' suffix in 'vpmu_intel.c' > > - add zero-padding to constants in 'vmx.h' > > - add missing 'U' in 'vmx.h' > > --- > > xen/arch/x86/cpu/vpmu_intel.c | 2 +- > > xen/arch/x86/hvm/vmx/vmcs.c | 6 +- > > xen/arch/x86/hvm/vmx/vvmx.c | 8 +-- > > xen/arch/x86/include/asm/hvm/vmx/vmcs.h | 84 ++++++++++++------------- > > xen/arch/x86/include/asm/hvm/vmx/vmx.h | 16 ++--- > > 5 files changed, 58 insertions(+), 58 deletions(-) > > > > diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c > > index fa5b40c65c..6330c89b47 100644 > > --- a/xen/arch/x86/cpu/vpmu_intel.c > > +++ b/xen/arch/x86/cpu/vpmu_intel.c > > @@ -945,7 +945,7 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) > > fixed_counters_mask = ~((1ull << core2_get_bitwidth_fix_count()) - 1); > > global_ctrl_mask = ~((((1ULL << fixed_pmc_cnt) - 1) << 32) | > > ((1ULL << arch_pmc_cnt) - 1)); > > - global_ovf_ctrl_mask = ~(0xC000000000000000 | > > + global_ovf_ctrl_mask = ~(0xC000000000000000ULL | > > (((1ULL << fixed_pmc_cnt) - 1) << 32) | > > ((1ULL << arch_pmc_cnt) - 1)); > > if ( version > 2 ) > > diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c > > index 13719cc923..6cefb88aec 100644 > > --- a/xen/arch/x86/hvm/vmx/vmcs.c > > +++ b/xen/arch/x86/hvm/vmx/vmcs.c > > @@ -911,7 +911,7 @@ void vmx_clear_msr_intercept(struct vcpu *v, > > unsigned int msr, > > if ( type & VMX_MSR_W ) > > clear_bit(msr, msr_bitmap->write_low); > > } > > - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) > > + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) > > { > > msr &= 0x1fff; > > if ( type & VMX_MSR_R ) > > @@ -939,7 +939,7 @@ void vmx_set_msr_intercept(struct vcpu *v, unsigned int > > msr, > > if ( type & VMX_MSR_W ) > > set_bit(msr, msr_bitmap->write_low); > > } > > - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) > > + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) > > { > > msr &= 0x1fff; > > if ( type & VMX_MSR_R ) > > @@ -957,7 +957,7 @@ bool vmx_msr_is_intercepted(struct vmx_msr_bitmap > > *msr_bitmap, > > if ( msr <= 0x1fff ) > > return test_bit(msr, is_write ? msr_bitmap->write_low > > : msr_bitmap->read_low); > > - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) > > + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) > > return test_bit(msr & 0x1fff, is_write ? msr_bitmap->write_high > > : msr_bitmap->read_high); > > else > > diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c > > index 16b0ef82b6..b7be424afb 100644 > > --- a/xen/arch/x86/hvm/vmx/vvmx.c > > +++ b/xen/arch/x86/hvm/vmx/vvmx.c > > @@ -263,7 +263,7 @@ uint64_t get_vvmcs_virtual(void *vvmcs, uint32_t > > vmcs_encoding) > > res >>= 32; > > break; > > case VVMCS_WIDTH_32: > > - res &= 0xffffffff; > > + res = (uint32_t)res; > > break; > > case VVMCS_WIDTH_NATURAL: > > default: > > @@ -315,14 +315,14 @@ void set_vvmcs_virtual(void *vvmcs, uint32_t > > vmcs_encoding, uint64_t val) > > case VVMCS_WIDTH_64: > > if ( enc.access_type ) > > { > > - res &= 0xffffffff; > > + res = (uint32_t)res; > > res |= val << 32; > > } > > else > > res = val; > > break; > > case VVMCS_WIDTH_32: > > - res = val & 0xffffffff; > > + res = (uint32_t)val; > > break; > > case VVMCS_WIDTH_NATURAL: > > default: > > @@ -2306,7 +2306,7 @@ int nvmx_msr_read_intercept(unsigned int msr, > > u64 *msr_content) > > break; > > case MSR_IA32_VMX_CR0_FIXED1: > > /* allow 0-settings for all bits */ > > - data = 0xffffffff; > > + data = 0xffffffffU; > > break; > > case MSR_IA32_VMX_CR4_FIXED0: > > /* VMXE bit must be 1 in VMX operation */ > > diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h > > b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h > > index d07fcb2bc9..e056643993 100644 > > --- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h > > +++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h > > @@ -187,27 +187,27 @@ bool_t __must_check vmx_vmcs_try_enter(struct vcpu > > *v); > > void vmx_vmcs_exit(struct vcpu *v); > > void vmx_vmcs_reload(struct vcpu *v); > > > > -#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 > > -#define CPU_BASED_USE_TSC_OFFSETING 0x00000008 > > -#define CPU_BASED_HLT_EXITING 0x00000080 > > -#define CPU_BASED_INVLPG_EXITING 0x00000200 > > -#define CPU_BASED_MWAIT_EXITING 0x00000400 > > -#define CPU_BASED_RDPMC_EXITING 0x00000800 > > -#define CPU_BASED_RDTSC_EXITING 0x00001000 > > -#define CPU_BASED_CR3_LOAD_EXITING 0x00008000 > > -#define CPU_BASED_CR3_STORE_EXITING 0x00010000 > > -#define CPU_BASED_CR8_LOAD_EXITING 0x00080000 > > -#define CPU_BASED_CR8_STORE_EXITING 0x00100000 > > -#define CPU_BASED_TPR_SHADOW 0x00200000 > > -#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 > > -#define CPU_BASED_MOV_DR_EXITING 0x00800000 > > -#define CPU_BASED_UNCOND_IO_EXITING 0x01000000 > > -#define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000 > > -#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 > > -#define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000 > > -#define CPU_BASED_MONITOR_EXITING 0x20000000 > > -#define CPU_BASED_PAUSE_EXITING 0x40000000 > > -#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 > > +#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004U > > +#define CPU_BASED_USE_TSC_OFFSETING 0x00000008U > > +#define CPU_BASED_HLT_EXITING 0x00000080U > > +#define CPU_BASED_INVLPG_EXITING 0x00000200U > > +#define CPU_BASED_MWAIT_EXITING 0x00000400U > > +#define CPU_BASED_RDPMC_EXITING 0x00000800U > > +#define CPU_BASED_RDTSC_EXITING 0x00001000U > > +#define CPU_BASED_CR3_LOAD_EXITING 0x00008000U > > +#define CPU_BASED_CR3_STORE_EXITING 0x00010000U > > +#define CPU_BASED_CR8_LOAD_EXITING 0x00080000U > > +#define CPU_BASED_CR8_STORE_EXITING 0x00100000U > > +#define CPU_BASED_TPR_SHADOW 0x00200000U > > +#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000U > > +#define CPU_BASED_MOV_DR_EXITING 0x00800000U > > +#define CPU_BASED_UNCOND_IO_EXITING 0x01000000U > > +#define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000U > > +#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000U > > +#define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000U > > +#define CPU_BASED_MONITOR_EXITING 0x20000000U > > +#define CPU_BASED_PAUSE_EXITING 0x40000000U > > +#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000U > > extern u32 vmx_cpu_based_exec_control; > > > > #define PIN_BASED_EXT_INTR_MASK 0x00000001 > > @@ -238,26 +238,26 @@ extern u32 vmx_vmexit_control; > > #define VM_ENTRY_LOAD_BNDCFGS 0x00010000 > > extern u32 vmx_vmentry_control; > > > > -#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 > > -#define SECONDARY_EXEC_ENABLE_EPT 0x00000002 > > -#define SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING 0x00000004 > > -#define SECONDARY_EXEC_ENABLE_RDTSCP 0x00000008 > > -#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 > > -#define SECONDARY_EXEC_ENABLE_VPID 0x00000020 > > -#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 > > -#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 > > -#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 > > -#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 > > -#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 > > -#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 > > -#define SECONDARY_EXEC_ENABLE_VM_FUNCTIONS 0x00002000 > > -#define SECONDARY_EXEC_ENABLE_VMCS_SHADOWING 0x00004000 > > -#define SECONDARY_EXEC_ENABLE_PML 0x00020000 > > -#define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000 > > -#define SECONDARY_EXEC_XSAVES 0x00100000 > > -#define SECONDARY_EXEC_TSC_SCALING 0x02000000 > > -#define SECONDARY_EXEC_BUS_LOCK_DETECTION 0x40000000 > > -#define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000 > > +#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001U > > +#define SECONDARY_EXEC_ENABLE_EPT 0x00000002U > > +#define SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING 0x00000004U > > +#define SECONDARY_EXEC_ENABLE_RDTSCP 0x00000008U > > +#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010U > > +#define SECONDARY_EXEC_ENABLE_VPID 0x00000020U > > +#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040U > > +#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080U > > +#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100U > > +#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200U > > +#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400U > > +#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000U > > +#define SECONDARY_EXEC_ENABLE_VM_FUNCTIONS 0x00002000U > > +#define SECONDARY_EXEC_ENABLE_VMCS_SHADOWING 0x00004000U > > +#define SECONDARY_EXEC_ENABLE_PML 0x00020000U > > +#define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000U > > +#define SECONDARY_EXEC_XSAVES 0x00100000U > > +#define SECONDARY_EXEC_TSC_SCALING 0x02000000U > > +#define SECONDARY_EXEC_BUS_LOCK_DETECTION 0x40000000U > > +#define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000U > > extern u32 vmx_secondary_exec_control; > > > > #define VMX_EPT_EXEC_ONLY_SUPPORTED 0x00000001 > > @@ -346,7 +346,7 @@ extern u64 vmx_ept_vpid_cap; > > #define cpu_has_vmx_notify_vm_exiting \ > > (vmx_secondary_exec_control & SECONDARY_EXEC_NOTIFY_VM_EXITING) > > > > -#define VMCS_RID_TYPE_MASK 0x80000000 > > +#define VMCS_RID_TYPE_MASK 0x80000000U > > > > /* GUEST_INTERRUPTIBILITY_INFO flags. */ > > #define VMX_INTR_SHADOW_STI 0x00000001 > > diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h > > b/xen/arch/x86/include/asm/hvm/vmx/vmx.h > > index c84acc221d..d4b335a2bc 100644 > > --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h > > +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h > > @@ -137,7 +137,7 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc) > > /* > > * Exit Reasons > > */ > > -#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000 > > +#define VMX_EXIT_REASONS_FAILED_VMENTRY (1u << 31) > > #define VMX_EXIT_REASONS_BUS_LOCK (1u << 26) > > > > #define EXIT_REASON_EXCEPTION_NMI 0 > > @@ -209,12 +209,12 @@ static inline void pi_clear_sn(struct pi_desc > > *pi_desc) > > * Note INTR_INFO_NMI_UNBLOCKED_BY_IRET is also used with Exit > > Qualification > > * field for EPT violations, PML full and SPP-related event vmexits. > > */ > > -#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ > > -#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ > > -#define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ > > -#define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x1000 /* 12 */ > > -#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ > > -#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000 > > +#define INTR_INFO_VECTOR_MASK 0x000000ffU /* 7:0 */ > > +#define INTR_INFO_INTR_TYPE_MASK 0x00000700U /* 10:8 */ > > +#define INTR_INFO_DELIVER_CODE_MASK 0x00000800U /* 11 */ > > +#define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x00001000U /* 12 */ > > +#define INTR_INFO_VALID_MASK 0x80000000U /* 31 */ > > +#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000U > > > > /* > > * Exit Qualifications for NOTIFY VM EXIT > > @@ -607,7 +607,7 @@ static inline void vmx_pi_hooks_assign(struct domain *d) > > {} > > static inline void vmx_pi_hooks_deassign(struct domain *d) {} > > #endif > > > > -#define APIC_INVALID_DEST 0xffffffff > > +#define APIC_INVALID_DEST 0xffffffffU > > > > /* EPT violation qualifications definitions */ > > typedef union ept_qual { > > I checked that this patch still applies cleanly on the current staging branch. > Can this get an ack from the VT-X maintainer(s)? Jan having acked this patch already, and the VT-X maintainers being not always fast in reviews, I imagine Jan will commit the patch on his own in a few days if nobody speaks up.
On 27 Jul 2023, Jan Beulich wrote: On 26.07.2023 13:03, Simone Ballarin wrote: > >* @@ -70,15 +70,15 @@ static const uint8_t sr_mask[8] = {* > >* };* > > > >* static const uint8_t gr_mask[9] = {* > >* - (uint8_t)~0xf0, /* 0x00 */* > >* - (uint8_t)~0xf0, /* 0x01 */* > >* - (uint8_t)~0xf0, /* 0x02 */* > >* - (uint8_t)~0xe0, /* 0x03 */* > >* - (uint8_t)~0xfc, /* 0x04 */* > >* - (uint8_t)~0x84, /* 0x05 */* > >* - (uint8_t)~0xf0, /* 0x06 */* > >* - (uint8_t)~0xf0, /* 0x07 */* > >* - (uint8_t)~0x00, /* 0x08 */* > >* + (uint8_t)~0xf0,* > >* + (uint8_t)~0xf0,* > >* + (uint8_t)~0xf0,* > >* + (uint8_t)~0xe0,* > >* + (uint8_t)~0xfc,* > >* + (uint8_t)~0x84,* > >* + (uint8_t)~0xf0,* > >* + (uint8_t)~0xf0,* > >* + (uint8_t)~0x00,* > >* };* > > Hmm, this stray change is _still_ there. > > Ok. Sorry for that. > >* --- a/xen/arch/x86/include/asm/hvm/trace.h* > >* +++ b/xen/arch/x86/include/asm/hvm/trace.h* > >* @@ -58,7 +58,7 @@* > >* #define DO_TRC_HVM_VLAPIC DEFAULT_HVM_MISC* > > > > > >* -#define TRC_PAR_LONG(par) ((par)&0xFFFFFFFF),((par)>>32)* > >* +#define TRC_PAR_LONG(par) ((uint32_t)par), ((par) >> 32)* > > You've lost parentheses around "par". > > >* @@ -93,7 +93,7 @@* > >* HVMTRACE_ND(evt, 0, 0)* > > > >* #define HVMTRACE_LONG_1D(evt, d1) \* > >* - HVMTRACE_2D(evt ## 64, (d1) & 0xFFFFFFFF, (d1) >> 32)* > >* + HVMTRACE_2D(evt ## 64, (uint32_t)d1, (d1) >> 32)* > > Same for "d1" here. > > Both of these are, btw., indications that you should have dropped Stefano's > R-b. > > Ok. > >* --- a/xen/arch/x86/include/asm/msr-index.h* > >* +++ b/xen/arch/x86/include/asm/msr-index.h* > >* @@ -30,7 +30,7 @@* > > > >* #define MSR_INTEL_CORE_THREAD_COUNT 0x00000035* > >* #define MSR_CTC_THREAD_MASK 0x0000ffff* > >* -#define MSR_CTC_CORE_MASK 0xffff0000* > >* +#define MSR_CTC_CORE_MASK 0xffff0000U* > > > >* #define MSR_SPEC_CTRL 0x00000048* > >* #define SPEC_CTRL_IBRS (_AC(1, ULL) << 0)* > >* @@ -168,7 +168,7 @@* > >* #define MSR_UARCH_MISC_CTRL 0x00001b01* > >* #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0)* > > > >* -#define MSR_EFER 0xc0000080 /* Extended Feature * > >* Enable Register */* > >* +#define MSR_EFER _AC(0xc0000080, U) /* Extended * > >* Feature Enable Register */* > > I understand you use _AC() here because the constant is used in assembly > code. But I don't understand why you use it only here, and not throughout > at least the "modern" portion of the file. I wonder what other x86 > maintainers think about this. > > I've used _AC only when strictly required to avoid errors. In v5 I will use _AC on all constants in the "modern" part of the file. > As a minor aspect, I also don't really see why you insert a 2nd blank > ahead of the comment. > > To align the comment with the others below. I see that comment aligning is not done in this file, so I will drop the change in v5. > >* #define EFER_SCE (_AC(1, ULL) << 0) /* SYSCALL * > >* Enable */* > >* #define EFER_LME (_AC(1, ULL) << 8) /* Long Mode * > >* Enable */* > >* #define EFER_LMA (_AC(1, ULL) << 10) /* Long Mode * > >* Active */* > >* @@ -181,35 +181,35 @@* > >* (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE | \* > >* EFER_AIBRSE)* > > > >* -#define MSR_STAR 0xc0000081 /* legacy mode * > >* SYSCALL target */* > >* -#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL * > >* target */* > >* -#define MSR_CSTAR 0xc0000083 /* compat mode * > >* SYSCALL target */* > >* -#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for * > >* syscall */* > >* -#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */* > >* -#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */* > >* -#define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */* > >* -#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */* > >* +#define MSR_STAR 0xc0000081U /* legacy mode * > >* SYSCALL target */* > >* +#define MSR_LSTAR 0xc0000082U /* long mode SYSCALL * > >* target */* > >* +#define MSR_CSTAR 0xc0000083U /* compat mode * > >* SYSCALL target */* > >* +#define MSR_SYSCALL_MASK 0xc0000084U /* EFLAGS mask for * > >* syscall */* > >* +#define MSR_FS_BASE 0xc0000100U /* 64bit FS base */* > >* +#define MSR_GS_BASE 0xc0000101U /* 64bit GS base */* > >* +#define MSR_SHADOW_GS_BASE 0xc0000102U /* SwapGS GS shadow * > >* */* > >* +#define MSR_TSC_AUX 0xc0000103U /* Auxiliary TSC */* > > > >* -#define MSR_K8_SYSCFG 0xc0010010* > >* +#define MSR_K8_SYSCFG 0xc0010010U* > >* #define SYSCFG_MTRR_FIX_DRAM_EN (_AC(1, ULL) << 18)* > >* #define SYSCFG_MTRR_FIX_DRAM_MOD_EN (_AC(1, ULL) << 19)* > >* #define SYSCFG_MTRR_VAR_DRAM_EN (_AC(1, ULL) << 20)* > >* #define SYSCFG_MTRR_TOM2_EN (_AC(1, ULL) << 21)* > >* #define SYSCFG_TOM2_FORCE_WB (_AC(1, ULL) << 22)* > > > >* -#define MSR_K8_IORR_BASE0 0xc0010016* > >* -#define MSR_K8_IORR_MASK0 0xc0010017* > >* -#define MSR_K8_IORR_BASE1 0xc0010018* > >* -#define MSR_K8_IORR_MASK1 0xc0010019* > >* +#define MSR_K8_IORR_BASE0 0xc0010016U* > >* +#define MSR_K8_IORR_MASK0 0xc0010017U* > >* +#define MSR_K8_IORR_BASE1 0xc0010018U* > >* +#define MSR_K8_IORR_MASK1 0xc0010019U* > > > >* -#define MSR_K8_TSEG_BASE 0xc0010112 /* AMD doc: SMMAddr */* > >* -#define MSR_K8_TSEG_MASK 0xc0010113 /* AMD doc: SMMMask */* > >* +#define MSR_K8_TSEG_BASE 0xc0010112U /* AMD doc: SMMAddr * > >* */* > >* +#define MSR_K8_TSEG_MASK 0xc0010113U /* AMD doc: SMMMask * > >* */* > > > >* -#define MSR_K8_VM_CR 0xc0010114* > >* +#define MSR_K8_VM_CR 0xc0010114U* > >* #define VM_CR_INIT_REDIRECTION (_AC(1, ULL) << 1)* > >* #define VM_CR_SVM_DISABLE (_AC(1, ULL) << 4)* > > > >* -#define MSR_VIRT_SPEC_CTRL 0xc001011f /* Layout matches * > >* MSR_SPEC_CTRL */* > >* +#define MSR_VIRT_SPEC_CTRL 0xc001011fU /* Layout matches * > >* MSR_SPEC_CTRL */* > > > >* /** > >* * Legacy MSR constants in need of cleanup. No new MSRs below this comment.* > > (As to above remark: This is the separator between "modern" [above] > and "historic" [below].) > > Jan > >
diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index fa5b40c65c..6330c89b47 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -945,7 +945,7 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) fixed_counters_mask = ~((1ull << core2_get_bitwidth_fix_count()) - 1); global_ctrl_mask = ~((((1ULL << fixed_pmc_cnt) - 1) << 32) | ((1ULL << arch_pmc_cnt) - 1)); - global_ovf_ctrl_mask = ~(0xC000000000000000 | + global_ovf_ctrl_mask = ~(0xC000000000000000ULL | (((1ULL << fixed_pmc_cnt) - 1) << 32) | ((1ULL << arch_pmc_cnt) - 1)); if ( version > 2 ) diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 13719cc923..6cefb88aec 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -911,7 +911,7 @@ void vmx_clear_msr_intercept(struct vcpu *v, unsigned int msr, if ( type & VMX_MSR_W ) clear_bit(msr, msr_bitmap->write_low); } - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) { msr &= 0x1fff; if ( type & VMX_MSR_R ) @@ -939,7 +939,7 @@ void vmx_set_msr_intercept(struct vcpu *v, unsigned int msr, if ( type & VMX_MSR_W ) set_bit(msr, msr_bitmap->write_low); } - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) { msr &= 0x1fff; if ( type & VMX_MSR_R ) @@ -957,7 +957,7 @@ bool vmx_msr_is_intercepted(struct vmx_msr_bitmap *msr_bitmap, if ( msr <= 0x1fff ) return test_bit(msr, is_write ? msr_bitmap->write_low : msr_bitmap->read_low); - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) return test_bit(msr & 0x1fff, is_write ? msr_bitmap->write_high : msr_bitmap->read_high); else diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 16b0ef82b6..b7be424afb 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -263,7 +263,7 @@ uint64_t get_vvmcs_virtual(void *vvmcs, uint32_t vmcs_encoding) res >>= 32; break; case VVMCS_WIDTH_32: - res &= 0xffffffff; + res = (uint32_t)res; break; case VVMCS_WIDTH_NATURAL: default: @@ -315,14 +315,14 @@ void set_vvmcs_virtual(void *vvmcs, uint32_t vmcs_encoding, uint64_t val) case VVMCS_WIDTH_64: if ( enc.access_type ) { - res &= 0xffffffff; + res = (uint32_t)res; res |= val << 32; } else res = val; break; case VVMCS_WIDTH_32: - res = val & 0xffffffff; + res = (uint32_t)val; break; case VVMCS_WIDTH_NATURAL: default: @@ -2306,7 +2306,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) break; case MSR_IA32_VMX_CR0_FIXED1: /* allow 0-settings for all bits */ - data = 0xffffffff; + data = 0xffffffffU; break; case MSR_IA32_VMX_CR4_FIXED0: /* VMXE bit must be 1 in VMX operation */ diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h index d07fcb2bc9..e056643993 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h @@ -187,27 +187,27 @@ bool_t __must_check vmx_vmcs_try_enter(struct vcpu *v); void vmx_vmcs_exit(struct vcpu *v); void vmx_vmcs_reload(struct vcpu *v); -#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 -#define CPU_BASED_USE_TSC_OFFSETING 0x00000008 -#define CPU_BASED_HLT_EXITING 0x00000080 -#define CPU_BASED_INVLPG_EXITING 0x00000200 -#define CPU_BASED_MWAIT_EXITING 0x00000400 -#define CPU_BASED_RDPMC_EXITING 0x00000800 -#define CPU_BASED_RDTSC_EXITING 0x00001000 -#define CPU_BASED_CR3_LOAD_EXITING 0x00008000 -#define CPU_BASED_CR3_STORE_EXITING 0x00010000 -#define CPU_BASED_CR8_LOAD_EXITING 0x00080000 -#define CPU_BASED_CR8_STORE_EXITING 0x00100000 -#define CPU_BASED_TPR_SHADOW 0x00200000 -#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 -#define CPU_BASED_MOV_DR_EXITING 0x00800000 -#define CPU_BASED_UNCOND_IO_EXITING 0x01000000 -#define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000 -#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 -#define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000 -#define CPU_BASED_MONITOR_EXITING 0x20000000 -#define CPU_BASED_PAUSE_EXITING 0x40000000 -#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 +#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004U +#define CPU_BASED_USE_TSC_OFFSETING 0x00000008U +#define CPU_BASED_HLT_EXITING 0x00000080U +#define CPU_BASED_INVLPG_EXITING 0x00000200U +#define CPU_BASED_MWAIT_EXITING 0x00000400U +#define CPU_BASED_RDPMC_EXITING 0x00000800U +#define CPU_BASED_RDTSC_EXITING 0x00001000U +#define CPU_BASED_CR3_LOAD_EXITING 0x00008000U +#define CPU_BASED_CR3_STORE_EXITING 0x00010000U +#define CPU_BASED_CR8_LOAD_EXITING 0x00080000U +#define CPU_BASED_CR8_STORE_EXITING 0x00100000U +#define CPU_BASED_TPR_SHADOW 0x00200000U +#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000U +#define CPU_BASED_MOV_DR_EXITING 0x00800000U +#define CPU_BASED_UNCOND_IO_EXITING 0x01000000U +#define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000U +#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000U +#define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000U +#define CPU_BASED_MONITOR_EXITING 0x20000000U +#define CPU_BASED_PAUSE_EXITING 0x40000000U +#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000U extern u32 vmx_cpu_based_exec_control; #define PIN_BASED_EXT_INTR_MASK 0x00000001 @@ -238,26 +238,26 @@ extern u32 vmx_vmexit_control; #define VM_ENTRY_LOAD_BNDCFGS 0x00010000 extern u32 vmx_vmentry_control; -#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 -#define SECONDARY_EXEC_ENABLE_EPT 0x00000002 -#define SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING 0x00000004 -#define SECONDARY_EXEC_ENABLE_RDTSCP 0x00000008 -#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 -#define SECONDARY_EXEC_ENABLE_VPID 0x00000020 -#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 -#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 -#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 -#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 -#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 -#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 -#define SECONDARY_EXEC_ENABLE_VM_FUNCTIONS 0x00002000 -#define SECONDARY_EXEC_ENABLE_VMCS_SHADOWING 0x00004000 -#define SECONDARY_EXEC_ENABLE_PML 0x00020000 -#define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000 -#define SECONDARY_EXEC_XSAVES 0x00100000 -#define SECONDARY_EXEC_TSC_SCALING 0x02000000 -#define SECONDARY_EXEC_BUS_LOCK_DETECTION 0x40000000 -#define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000 +#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001U +#define SECONDARY_EXEC_ENABLE_EPT 0x00000002U +#define SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING 0x00000004U +#define SECONDARY_EXEC_ENABLE_RDTSCP 0x00000008U +#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010U +#define SECONDARY_EXEC_ENABLE_VPID 0x00000020U +#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040U +#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080U +#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100U +#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200U +#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400U +#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000U +#define SECONDARY_EXEC_ENABLE_VM_FUNCTIONS 0x00002000U +#define SECONDARY_EXEC_ENABLE_VMCS_SHADOWING 0x00004000U +#define SECONDARY_EXEC_ENABLE_PML 0x00020000U +#define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000U +#define SECONDARY_EXEC_XSAVES 0x00100000U +#define SECONDARY_EXEC_TSC_SCALING 0x02000000U +#define SECONDARY_EXEC_BUS_LOCK_DETECTION 0x40000000U +#define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000U extern u32 vmx_secondary_exec_control; #define VMX_EPT_EXEC_ONLY_SUPPORTED 0x00000001 @@ -346,7 +346,7 @@ extern u64 vmx_ept_vpid_cap; #define cpu_has_vmx_notify_vm_exiting \ (vmx_secondary_exec_control & SECONDARY_EXEC_NOTIFY_VM_EXITING) -#define VMCS_RID_TYPE_MASK 0x80000000 +#define VMCS_RID_TYPE_MASK 0x80000000U /* GUEST_INTERRUPTIBILITY_INFO flags. */ #define VMX_INTR_SHADOW_STI 0x00000001 diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h b/xen/arch/x86/include/asm/hvm/vmx/vmx.h index c84acc221d..d4b335a2bc 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h @@ -137,7 +137,7 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc) /* * Exit Reasons */ -#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000 +#define VMX_EXIT_REASONS_FAILED_VMENTRY (1u << 31) #define VMX_EXIT_REASONS_BUS_LOCK (1u << 26) #define EXIT_REASON_EXCEPTION_NMI 0 @@ -209,12 +209,12 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc) * Note INTR_INFO_NMI_UNBLOCKED_BY_IRET is also used with Exit Qualification * field for EPT violations, PML full and SPP-related event vmexits. */ -#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ -#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ -#define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ -#define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x1000 /* 12 */ -#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ -#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000 +#define INTR_INFO_VECTOR_MASK 0x000000ffU /* 7:0 */ +#define INTR_INFO_INTR_TYPE_MASK 0x00000700U /* 10:8 */ +#define INTR_INFO_DELIVER_CODE_MASK 0x00000800U /* 11 */ +#define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x00001000U /* 12 */ +#define INTR_INFO_VALID_MASK 0x80000000U /* 31 */ +#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000U /* * Exit Qualifications for NOTIFY VM EXIT @@ -607,7 +607,7 @@ static inline void vmx_pi_hooks_assign(struct domain *d) {} static inline void vmx_pi_hooks_deassign(struct domain *d) {} #endif -#define APIC_INVALID_DEST 0xffffffff +#define APIC_INVALID_DEST 0xffffffffU /* EPT violation qualifications definitions */ typedef union ept_qual {