From patchwork Thu Apr 4 13:46:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pu Wen X-Patchwork-Id: 10885635 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E10E0139A for ; Thu, 4 Apr 2019 13:51:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C9DC1284CE for ; Thu, 4 Apr 2019 13:51:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BD7D628712; Thu, 4 Apr 2019 13:51:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4AC09284CE for ; Thu, 4 Apr 2019 13:51:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hC2ki-0007Ki-53; Thu, 04 Apr 2019 13:50:00 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hC2kg-0007KR-IT for xen-devel@lists.xenproject.org; Thu, 04 Apr 2019 13:49:58 +0000 X-Inumbo-ID: 867e48eb-56e0-11e9-92d7-bc764e045a96 Received: from spam1.hygon.cn (unknown [110.188.70.11]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 867e48eb-56e0-11e9-92d7-bc764e045a96; Thu, 04 Apr 2019 13:49:56 +0000 (UTC) Received: from MK-FE.hygon.cn ([172.23.18.61]) by spam1.hygon.cn with ESMTP id x34DkXQg097099; Thu, 4 Apr 2019 21:46:33 +0800 (GMT-8) (envelope-from puwen@hygon.cn) Received: from cncheex01.Hygon.cn ([172.23.18.10]) by MK-FE.hygon.cn with ESMTP id x34DkD3K063256; Thu, 4 Apr 2019 21:46:13 +0800 (GMT-8) (envelope-from puwen@hygon.cn) Received: from pw-vbox.hygon.cn (172.23.18.44) by cncheex01.Hygon.cn (172.23.18.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1466.3; Thu, 4 Apr 2019 21:46:30 +0800 From: Pu Wen To: Date: Thu, 4 Apr 2019 21:46:23 +0800 Message-ID: <77e68211d0a9329370bc12eaf5e741bef86a92b1.1554382869.git.puwen@hygon.cn> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [172.23.18.44] X-ClientProxiedBy: cncheex01.Hygon.cn (172.23.18.10) To cncheex01.Hygon.cn (172.23.18.10) X-MAIL: spam1.hygon.cn x34DkXQg097099 X-DNSRBL: Subject: [Xen-devel] [PATCH v5 05/15] x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Pu Wen , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Jan Beulich , Andrew Cooper Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The machine check architecture for Hygon Dhyana CPU is similar to the AMD family 17h one. Add vendor checking for Hygon Dhyana to share the code path of AMD family 17h. Signed-off-by: Pu Wen Acked-by: Jan Beulich --- xen/arch/x86/cpu/common.c | 3 ++- xen/arch/x86/cpu/mcheck/amd_nonfatal.c | 5 +++-- xen/arch/x86/cpu/mcheck/mce.c | 6 ++++-- xen/arch/x86/cpu/mcheck/mce_amd.c | 5 ++++- xen/arch/x86/cpu/mcheck/non-fatal.c | 3 ++- xen/arch/x86/cpu/mcheck/vmce.c | 2 ++ 6 files changed, 17 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 1a095fc..c14ff1b 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -326,7 +326,8 @@ static void __init early_cpu_detect(void) hap_paddr_bits = PADDR_BITS; } - if (c->x86_vendor != X86_VENDOR_AMD) + if (c->x86_vendor != X86_VENDOR_AMD && + c->x86_vendor != X86_VENDOR_HYGON) park_offline_cpus = opt_mce; initialize_cpu_data(0); diff --git a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c index 222f539..589dac5 100644 --- a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c +++ b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c @@ -203,10 +203,11 @@ static void mce_amd_work_fn(void *data) void __init amd_nonfatal_mcheck_init(struct cpuinfo_x86 *c) { - if (c->x86_vendor != X86_VENDOR_AMD) + if (c->x86_vendor != X86_VENDOR_AMD && + c->x86_vendor != X86_VENDOR_HYGON) return; - /* Assume we are on K8 or newer AMD CPU here */ + /* Assume we are on K8 or newer AMD or Hygon CPU here */ /* The threshold bitfields in MSR_IA32_MC4_MISC has * been introduced along with the SVME feature bit. */ diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index 30cdb06..0798dea 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -778,6 +778,7 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp) switch ( c->x86_vendor ) { case X86_VENDOR_AMD: + case X86_VENDOR_HYGON: inited = amd_mcheck_init(c); break; @@ -1172,10 +1173,11 @@ static bool x86_mc_msrinject_verify(struct xen_mc_msrinject *mci) /* MSRs that the HV will take care of */ case MSR_K8_HWCR: - if ( c->x86_vendor == X86_VENDOR_AMD ) + if ( c->x86_vendor == X86_VENDOR_AMD || + c->x86_vendor == X86_VENDOR_HYGON ) reason = "HV will operate HWCR"; else - reason = "only supported on AMD"; + reason = "only supported on AMD or Hygon"; break; default: diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c b/xen/arch/x86/cpu/mcheck/mce_amd.c index ed29fcc..8ed2b17 100644 --- a/xen/arch/x86/cpu/mcheck/mce_amd.c +++ b/xen/arch/x86/cpu/mcheck/mce_amd.c @@ -286,7 +286,10 @@ enum mcheck_type amd_mcheck_init(struct cpuinfo_x86 *ci) { uint32_t i; - enum mcequirk_amd_flags quirkflag = mcequirk_lookup_amd_quirkdata(ci); + enum mcequirk_amd_flags quirkflag = 0; + + if (ci->x86_vendor != X86_VENDOR_HYGON) + quirkflag = mcequirk_lookup_amd_quirkdata(ci); /* Assume that machine check support is available. * The minimum provided support is at least the K8. */ diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c b/xen/arch/x86/cpu/mcheck/non-fatal.c index d12e8f2..77be418 100644 --- a/xen/arch/x86/cpu/mcheck/non-fatal.c +++ b/xen/arch/x86/cpu/mcheck/non-fatal.c @@ -101,7 +101,8 @@ static int __init init_nonfatal_mce_checker(void) */ switch (c->x86_vendor) { case X86_VENDOR_AMD: - /* Assume we are on K8 or newer AMD CPU here */ + case X86_VENDOR_HYGON: + /* Assume we are on K8 or newer AMD or Hygon CPU here */ amd_nonfatal_mcheck_init(c); break; diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index f15835e..4f5de07 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -154,6 +154,7 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) break; case X86_VENDOR_AMD: + case X86_VENDOR_HYGON: ret = vmce_amd_rdmsr(v, msr, val); break; @@ -284,6 +285,7 @@ static int bank_mce_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) break; case X86_VENDOR_AMD: + case X86_VENDOR_HYGON: ret = vmce_amd_wrmsr(v, msr, val); break;