| Message ID | 7b03dbf21718ed9c05859a629f4442167d74553c.1683824347.git.oleksii.kurochko@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | enable MMU for RISC-V | expand |
On 11.05.2023 19:09, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/include/asm/config.h > +++ b/xen/arch/riscv/include/asm/config.h > @@ -4,6 +4,42 @@ > #include <xen/const.h> > #include <xen/page-size.h> > > +/* > + * RISC-V64 Layout: > + * > + * #ifdef SV39 I did point you at x86'es similar #ifdef. Unlike here, there we use a symbol which actually has a meaning, allowing to spot this comment in e.g. grep output when looking for uses of that symbol. Hence here e.g. #ifdef RV_STAGE1_MODE == SATP_MODE_SV39 ? (I would also recommend to use the same style as x86 does, such that the #ifdef and #endif look like normal directives [e.g. again in grep output], leaving aside that they're inside a comment.) > + * From the riscv-privileged doc: > + * When mapping between narrower and wider addresses, > + * RISC-V zero-extends a narrower physical address to a wider size. > + * The mapping between 64-bit virtual addresses and the 39-bit usable > + * address space of Sv39 is not based on zero-extension but instead > + * follows an entrenched convention that allows an OS to use one or > + * a few of the most-significant bits of a full-size (64-bit) virtual > + * address to quickly distinguish user and supervisor address regions. > + * > + * It means that: > + * top VA bits are simply ignored for the purpose of translating to PA. > + * > + * ============================================================================ > + * Start addr | End addr | Size | Slot |area description > + * ============================================================================ > + * FFFFFFFFC0800000 | FFFFFFFFFFFFFFFF |1016 MB | L2 511 | Unused > + * FFFFFFFFC0600000 | FFFFFFFFC0800000 | 2 MB | L2 511 | Fixmap > + * FFFFFFFFC0200000 | FFFFFFFFC0600000 | 4 MB | L2 511 | FDT > + * FFFFFFFFC0000000 | FFFFFFFFC0200000 | 2 MB | L2 511 | Xen > + * ... | 1 GB | L2 510 | Unused > + * 0000003200000000 | 0000007f40000000 | 309 GB | L2 200-509 | Direct map The upper bound here is 0000007f80000000 afaict, which then also makes the earlier gap 1Gb in size. Jan
On Tue, 2023-05-16 at 17:42 +0200, Jan Beulich wrote: > On 11.05.2023 19:09, Oleksii Kurochko wrote: > > --- a/xen/arch/riscv/include/asm/config.h > > +++ b/xen/arch/riscv/include/asm/config.h > > @@ -4,6 +4,42 @@ > > #include <xen/const.h> > > #include <xen/page-size.h> > > > > +/* > > + * RISC-V64 Layout: > > + * > > + * #ifdef SV39 > > I did point you at x86'es similar #ifdef. Unlike here, there we use a > symbol which actually has a meaning, allowing to spot this comment in > e.g. grep output when looking for uses of that symbol. Hence here > e.g. > > #ifdef RV_STAGE1_MODE == SATP_MODE_SV39 > > ? (I would also recommend to use the same style as x86 does, such > that > the #ifdef and #endif look like normal directives [e.g. again in grep > output], leaving aside that they're inside a comment.) It would be better. Thanks. > > > + * From the riscv-privileged doc: > > + * When mapping between narrower and wider addresses, > > + * RISC-V zero-extends a narrower physical address to a wider > > size. > > + * The mapping between 64-bit virtual addresses and the 39-bit > > usable > > + * address space of Sv39 is not based on zero-extension but > > instead > > + * follows an entrenched convention that allows an OS to use one > > or > > + * a few of the most-significant bits of a full-size (64-bit) > > virtual > > + * address to quickly distinguish user and supervisor address > > regions. > > + * > > + * It means that: > > + * top VA bits are simply ignored for the purpose of translating > > to PA. > > + * > > + * > > =================================================================== > > ========= > > + * Start addr | End addr | Size | Slot > > |area description > > + * > > =================================================================== > > ========= > > + * FFFFFFFFC0800000 | FFFFFFFFFFFFFFFF |1016 MB | L2 511 | > > Unused > > + * FFFFFFFFC0600000 | FFFFFFFFC0800000 | 2 MB | L2 511 | > > Fixmap > > + * FFFFFFFFC0200000 | FFFFFFFFC0600000 | 4 MB | L2 511 | > > FDT > > + * FFFFFFFFC0000000 | FFFFFFFFC0200000 | 2 MB | L2 511 | > > Xen > > + * ... | 1 GB | L2 510 | > > Unused > > + * 0000003200000000 | 0000007f40000000 | 309 GB | L2 200-509 | > > Direct map > > The upper bound here is 0000007f80000000 afaict, It should be 0000007f80000000. 0000007f40000000 is start address of 509 slot. > which then also makes > the earlier gap 1Gb in size. do you mean that it is better to write start and end address ( 0000007f80000000 - 7FC0000000 ) of L2 510 slot explicitly? ~ Oleksii
On 17.05.2023 17:56, Oleksii wrote: > On Tue, 2023-05-16 at 17:42 +0200, Jan Beulich wrote: >> On 11.05.2023 19:09, Oleksii Kurochko wrote: >>> =================================================================== >>> ========= >>> + * Start addr | End addr | Size | Slot >>> |area description >>> + * >>> =================================================================== >>> ========= >>> + * FFFFFFFFC0800000 | FFFFFFFFFFFFFFFF |1016 MB | L2 511 | >>> Unused >>> + * FFFFFFFFC0600000 | FFFFFFFFC0800000 | 2 MB | L2 511 | >>> Fixmap >>> + * FFFFFFFFC0200000 | FFFFFFFFC0600000 | 4 MB | L2 511 | >>> FDT >>> + * FFFFFFFFC0000000 | FFFFFFFFC0200000 | 2 MB | L2 511 | >>> Xen >>> + * ... | 1 GB | L2 510 | >>> Unused >>> + * 0000003200000000 | 0000007f40000000 | 309 GB | L2 200-509 | >>> Direct map >> >> The upper bound here is 0000007f80000000 afaict, > It should be 0000007f80000000. 0000007f40000000 is start address of 509 > slot. > >> which then also makes >> the earlier gap 1Gb in size. > do you mean that it is better to write start and end address ( > 0000007f80000000 - 7FC0000000 ) of L2 510 slot explicitly? No, not really. The ... there is quite okay imo, because of the differing upper bits. I was merely pointing out that as you had it the gap was 2Gb (from 0000007f40000000 till FFFFFFFFC0000000, leaving aside the ignored upper bits). Jan
diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/asm/config.h index 763a922a04..a53833afee 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -4,6 +4,42 @@ #include <xen/const.h> #include <xen/page-size.h> +/* + * RISC-V64 Layout: + * + * #ifdef SV39 + * + * From the riscv-privileged doc: + * When mapping between narrower and wider addresses, + * RISC-V zero-extends a narrower physical address to a wider size. + * The mapping between 64-bit virtual addresses and the 39-bit usable + * address space of Sv39 is not based on zero-extension but instead + * follows an entrenched convention that allows an OS to use one or + * a few of the most-significant bits of a full-size (64-bit) virtual + * address to quickly distinguish user and supervisor address regions. + * + * It means that: + * top VA bits are simply ignored for the purpose of translating to PA. + * + * ============================================================================ + * Start addr | End addr | Size | Slot |area description + * ============================================================================ + * FFFFFFFFC0800000 | FFFFFFFFFFFFFFFF |1016 MB | L2 511 | Unused + * FFFFFFFFC0600000 | FFFFFFFFC0800000 | 2 MB | L2 511 | Fixmap + * FFFFFFFFC0200000 | FFFFFFFFC0600000 | 4 MB | L2 511 | FDT + * FFFFFFFFC0000000 | FFFFFFFFC0200000 | 2 MB | L2 511 | Xen + * ... | 1 GB | L2 510 | Unused + * 0000003200000000 | 0000007f40000000 | 309 GB | L2 200-509 | Direct map + * ... | 1 GB | L2 199 | Unused + * 0000003100000000 | 00000031C0000000 | 3 GB | L2 196-198 | Frametable + * ... | 1 GB | L2 195 | Unused + * 0000003080000000 | 00000030C0000000 | 1 GB | L2 194 | VMAP + * ... | 194 GB | L2 0 - 193 | Unused + * ============================================================================ + * + * #endif + */ + #if defined(CONFIG_RISCV_64) # define LONG_BYTEORDER 3 # define ELFSIZE 64
Also it was added explanation about ignoring of top VA bits Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> --- Changes in V7: - Fix range of frametable range in RV64 layout. - Add ifdef SV39 to the RV64 layout comment to make it explicit that description if for SV39 mode. - Add missed row in the RV64 layout table. --- Changes in V6: - update comment above the RISCV-64 layout table - add Slot column to the table with RISCV-64 Layout - update RV-64 layout table. --- Changes in V5: * the patch was introduced in the current patch series. --- xen/arch/riscv/include/asm/config.h | 36 +++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)