Message ID | 8ab32f85-d0d5-956d-9375-829e578c65d5@suse.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show
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x86: assorted shadow mode adjustments
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expand
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--- a/xen/arch/x86/mm/shadow/multi.c +++ b/xen/arch/x86/mm/shadow/multi.c @@ -91,6 +91,8 @@ const char *const fetch_type_names[] = { # define for_each_shadow_table(v, i) for ( (i) = 0; (i) < 1; ++(i) ) #endif +static void cf_check sh_update_cr3(struct vcpu *v, int do_locking, bool noflush); + /* Helper to perform a local TLB flush. */ static void sh_flush_local(const struct domain *d) { @@ -2487,7 +2489,7 @@ static int cf_check sh_page_fault( * In any case, in the PAE case, the ASSERT is not true; it can * happen because of actions the guest is taking. */ #if GUEST_PAGING_LEVELS == 3 - v->arch.paging.mode->update_cr3(v, 0, false); + sh_update_cr3(v, 0, false); #else ASSERT(d->is_shutting_down); #endif
There's no need for an indirect call here, as the mode is invariant throughout the entire paging-locked region. All it takes to avoid it is to have a forward declaration of sh_update_cr3() in place. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- I find this and the respective Win7 related comment suspicious: If we really need to "fix up" L3 entries "on demand", wouldn't we better retry the shadow_get_and_create_l1e() rather than exit? The spurious page fault that the guest observes can, after all, not be known to be non- fatal inside the guest. That's purely an OS policy. Furthermore the sh_update_cr3() will also invalidate L3 entries which were loaded successfully before, but invalidated by the guest afterwards. I strongly suspect that the described hardware behavior is _only_ to load previously not-present entries from the PDPT, but not purge ones already marked present. IOW I think sh_update_cr3() would need calling in an "incremental" mode here. (The alternative of doing this in shadow_get_and_create_l3e() instead would likely be more cumbersome.) Beyond the "on demand" L3 entry creation I also can't see what guest actions could lead to the ASSERT() being inapplicable in the PAE case. The 3-level code in shadow_get_and_create_l2e() doesn't consult guest PDPTEs, and all other logic is similar to that for other modes. (See 89329d832aed ["x86 shadow: Update cr3 in PAE mode when guest walk succeed but shadow walk fails"].)