| Message ID | 94a46f35bc9387c699d9d24b1c792b54ec290255.1675779308.git.oleksii.kurochko@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISCV basic exception handling implementation | expand |
On 07.02.2023 15:46, Oleksii Kurochko wrote: > --- /dev/null > +++ b/xen/arch/riscv/include/asm/csr.h > @@ -0,0 +1,84 @@ > +/* > + * SPDX-License-Identifier: GPL-2.0-only > + * > + * Copyright (C) 2015 Regents of the University of California > + */ > + > +#ifndef _ASM_RISCV_CSR_H > +#define _ASM_RISCV_CSR_H > + > +#include <asm/asm.h> > +#include <xen/const.h> > +#include <asm/riscv_encoding.h> > + > +#ifndef __ASSEMBLY__ > + > +#define csr_read(csr) \ > +({ \ > + register unsigned long __v; \ > + __asm__ __volatile__ ( "csrr %0, " __ASM_STR(csr) \ Nit: There's now one too many space (here and elsewhere below) between the opening parenthesis and the opening double quote. > +#define csr_clear(csr, val) \ > +({ \ > + unsigned long __v = (unsigned long)(val); \ > + __asm__ __volatile__ ( "csrc " __ASM_STR(csr) ", %0" \ > + : /*no outputs */ \ Nit: Missing blank inside comment. I think these adjustments could be done while committing, assuming no other changes are necessary and an ack appears. Jan
On Wed, Feb 8, 2023 at 12:47 AM Oleksii Kurochko <oleksii.kurochko@gmail.com> wrote: > > The following changes were made in comparison with <asm/csr.h> from > Linux: > * remove all defines as they are defined in riscv_encoding.h > * leave only csr_* macros > > Origin: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ d2d11f342b17 > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > Changes in V3: > - Update origin to https://git.kernel.org/... > --- > Changes in V2: > - Minor refactoring mentioned in the commit message, switch tabs to > spaces and refactor things around __asm__ __volatile__. > - Update the commit message and add "Origin:" tag. > --- > xen/arch/riscv/include/asm/csr.h | 84 ++++++++++++++++++++++++++++++++ > 1 file changed, 84 insertions(+) > create mode 100644 xen/arch/riscv/include/asm/csr.h > > diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/csr.h > new file mode 100644 > index 0000000000..4275cf6515 > --- /dev/null > +++ b/xen/arch/riscv/include/asm/csr.h > @@ -0,0 +1,84 @@ > +/* > + * SPDX-License-Identifier: GPL-2.0-only > + * > + * Copyright (C) 2015 Regents of the University of California > + */ > + > +#ifndef _ASM_RISCV_CSR_H > +#define _ASM_RISCV_CSR_H > + > +#include <asm/asm.h> > +#include <xen/const.h> > +#include <asm/riscv_encoding.h> > + > +#ifndef __ASSEMBLY__ > + > +#define csr_read(csr) \ > +({ \ > + register unsigned long __v; \ > + __asm__ __volatile__ ( "csrr %0, " __ASM_STR(csr) \ > + : "=r" (__v) \ > + : : "memory" ); \ > + __v; \ > +}) > + > +#define csr_write(csr, val) \ > +({ \ > + unsigned long __v = (unsigned long)(val); \ > + __asm__ __volatile__ ( "csrw " __ASM_STR(csr) ", %0" \ > + : /* no outputs */ \ > + : "rK" (__v) \ > + : "memory" ); \ > +}) > + > +#define csr_swap(csr, val) \ > +({ \ > + unsigned long __v = (unsigned long)(val); \ > + __asm__ __volatile__ ( "csrrw %0, " __ASM_STR(csr) ", %1" \ > + : "=r" (__v) \ > + : "rK" (__v) \ > + : "memory" ); \ > + __v; \ > +}) > + > +#define csr_read_set(csr, val) \ > +({ \ > + unsigned long __v = (unsigned long)(val); \ > + __asm__ __volatile__ ( "csrrs %0, " __ASM_STR(csr) ", %1" \ > + : "=r" (__v) \ > + : "rK" (__v) \ > + : "memory" ); \ > + __v; \ > +}) > + > +#define csr_set(csr, val) \ > +({ \ > + unsigned long __v = (unsigned long)(val); \ > + __asm__ __volatile__ ( "csrs " __ASM_STR(csr) ", %0" \ > + : /* no outputs */ \ > + : "rK" (__v) \ > + : "memory" ); \ > +}) > + > +#define csr_read_clear(csr, val) \ > +({ \ > + unsigned long __v = (unsigned long)(val); \ > + __asm__ __volatile__ ( "csrrc %0, " __ASM_STR(csr) ", %1" \ > + : "=r" (__v) \ > + : "rK" (__v) \ > + : "memory" ); \ > + __v; \ > +}) > + > +#define csr_clear(csr, val) \ > +({ \ > + unsigned long __v = (unsigned long)(val); \ > + __asm__ __volatile__ ( "csrc " __ASM_STR(csr) ", %0" \ > + : /*no outputs */ \ > + : "rK" (__v) \ > + : "memory" ); \ > +}) > + > +#endif /* __ASSEMBLY__ */ > + > +#endif /* _ASM_RISCV_CSR_H */ > -- > 2.39.0 > >
diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/csr.h new file mode 100644 index 0000000000..4275cf6515 --- /dev/null +++ b/xen/arch/riscv/include/asm/csr.h @@ -0,0 +1,84 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (C) 2015 Regents of the University of California + */ + +#ifndef _ASM_RISCV_CSR_H +#define _ASM_RISCV_CSR_H + +#include <asm/asm.h> +#include <xen/const.h> +#include <asm/riscv_encoding.h> + +#ifndef __ASSEMBLY__ + +#define csr_read(csr) \ +({ \ + register unsigned long __v; \ + __asm__ __volatile__ ( "csrr %0, " __ASM_STR(csr) \ + : "=r" (__v) \ + : : "memory" ); \ + __v; \ +}) + +#define csr_write(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ( "csrw " __ASM_STR(csr) ", %0" \ + : /* no outputs */ \ + : "rK" (__v) \ + : "memory" ); \ +}) + +#define csr_swap(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ( "csrrw %0, " __ASM_STR(csr) ", %1" \ + : "=r" (__v) \ + : "rK" (__v) \ + : "memory" ); \ + __v; \ +}) + +#define csr_read_set(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ( "csrrs %0, " __ASM_STR(csr) ", %1" \ + : "=r" (__v) \ + : "rK" (__v) \ + : "memory" ); \ + __v; \ +}) + +#define csr_set(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ( "csrs " __ASM_STR(csr) ", %0" \ + : /* no outputs */ \ + : "rK" (__v) \ + : "memory" ); \ +}) + +#define csr_read_clear(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ( "csrrc %0, " __ASM_STR(csr) ", %1" \ + : "=r" (__v) \ + : "rK" (__v) \ + : "memory" ); \ + __v; \ +}) + +#define csr_clear(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ( "csrc " __ASM_STR(csr) ", %0" \ + : /*no outputs */ \ + : "rK" (__v) \ + : "memory" ); \ +}) + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_CSR_H */
The following changes were made in comparison with <asm/csr.h> from Linux: * remove all defines as they are defined in riscv_encoding.h * leave only csr_* macros Origin: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ d2d11f342b17 Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> --- Changes in V3: - Update origin to https://git.kernel.org/... --- Changes in V2: - Minor refactoring mentioned in the commit message, switch tabs to spaces and refactor things around __asm__ __volatile__. - Update the commit message and add "Origin:" tag. --- xen/arch/riscv/include/asm/csr.h | 84 ++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 xen/arch/riscv/include/asm/csr.h