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banners=-,-,- X-VirusChecked: Checked Received: (qmail 58602 invoked from network); 17 Feb 2017 09:38:02 -0000 Received: from szxga02-in.huawei.com (HELO szxga02-in.huawei.com) (119.145.14.65) by server-16.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 17 Feb 2017 09:38:02 -0000 Received: from 172.24.1.137 (EHLO SZXEMI413-HUB.china.huawei.com) ([172.24.1.137]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DUQ04099; Fri, 17 Feb 2017 17:37:55 +0800 (CST) Received: from SZXEMI506-MBX.china.huawei.com ([169.254.5.247]) by SZXEMI413-HUB.china.huawei.com ([10.86.210.41]) with mapi id 14.03.0235.001; Fri, 17 Feb 2017 17:37:45 +0800 From: "Xuquan (Quan Xu)" To: "xen-devel@lists.xen.org" Thread-Topic: [PATCH] x86/apicv: enhance posted-interrupt processing Thread-Index: AdKJAQ9UrmEB5HeDSQ+kneU/RFwMxA== Date: Fri, 17 Feb 2017 09:37:45 +0000 Message-ID: Accept-Language: en-US Content-Language: zh-CN X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [10.142.69.246] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0203.58A6C474.0164, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=169.254.5.247, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 72a99684a4e1b501fa467b11653c69e2 Cc: "yang.zhang.wz@gmail.com" , "Tian, Kevin" , "quan.xu0@gmail.com" , Jan Beulich , Andrew Cooper , Jun Nakajima , "Gao, Chao" Subject: [Xen-devel] [PATCH] x86/apicv: enhance posted-interrupt processing X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From a589074281cc22a30ed75a5bccba60e83d2312a6 Mon Sep 17 00:00:00 2001 From: Quan Xu Date: Sat, 18 Feb 2017 09:27:37 +0800 Subject: [PATCH] x86/apicv: enhance posted-interrupt processing If guest is already in non-root mode, an posted interrupt will be directly delivered to guest (leaving softirq being set w/o actually incurring a VM-Exit - breaking desired softirq behavior). Then further posted interrupts will skip the IPI, stay in PIR and not noted until another VM-Exit happens. Remove the softirq set. Actually since it's an optimization for less IPIs, check softirq_pending(cpu) directly instead of sticking to one bit only. Signed-off-by: Quan Xu --- xen/arch/x86/hvm/vmx/vmx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 1.8.3.1 diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 61925cf..3887c32 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -1846,8 +1846,7 @@ static void __vmx_deliver_posted_interrupt(struct vcpu *v) { unsigned int cpu = v->processor; - if ( !test_and_set_bit(VCPU_KICK_SOFTIRQ, &softirq_pending(cpu)) - && (cpu != smp_processor_id()) ) + if ( !softirq_pending(cpu) && (cpu != smp_processor_id()) ) send_IPI_mask(cpumask_of(cpu), posted_intr_vector); } }