@@ -2797,7 +2797,7 @@ static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
static const MemoryRegionOps notdirty_mem_ops = {
.write = notdirty_mem_write,
.valid.accepts = notdirty_mem_accepts,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 8,
@@ -2926,7 +2926,7 @@ static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
static const MemoryRegionOps watch_mem_ops = {
.read_with_attrs = watch_mem_read,
.write_with_attrs = watch_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 8,
@@ -3002,7 +3002,7 @@ static const MemoryRegionOps subpage_ops = {
.valid.min_access_size = 1,
.valid.max_access_size = 8,
.valid.accepts = subpage_accepts,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
@@ -3077,7 +3077,7 @@ static bool readonly_mem_accepts(void *opaque, hwaddr addr,
static const MemoryRegionOps readonly_mem_ops = {
.write = readonly_mem_write,
.valid.accepts = readonly_mem_accepts,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 8,
@@ -245,7 +245,7 @@ static void stm32f2xx_adc_write(void *opaque, hwaddr addr,
static const MemoryRegionOps stm32f2xx_adc_ops = {
.read = stm32f2xx_adc_read,
.write = stm32f2xx_adc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_stm32f2xx_adc = {
@@ -116,7 +116,7 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
/* FIXME use a qdev chardev prop instead of serial_hd() */
serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
- 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ 115200, serial_hd(0), MO_TE);
}
static void aw_a10_class_init(ObjectClass *oc, void *data)
@@ -88,7 +88,7 @@ static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
static const MemoryRegionOps bitband_ops = {
.read_with_attrs = bitband_read,
.write_with_attrs = bitband_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl.min_access_size = 1,
.impl.max_access_size = 4,
.valid.min_access_size = 1,
@@ -106,7 +106,7 @@ static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
static const MemoryRegionOps max_ram_ops = {
.read = max_ram_read,
.write = max_ram_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
#define FIRMWARE_ADDR 0x0
@@ -121,7 +121,7 @@ static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
.read = exynos4210_chipid_and_omr_read,
.write = exynos4210_chipid_and_omr_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
.max_access_size = 1,
}
@@ -150,7 +150,7 @@ static uint64_t hb_regs_read(void *opaque, hwaddr offset,
static const MemoryRegionOps hb_mem_ops = {
.read = hb_regs_read,
.write = hb_regs_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
@@ -263,7 +263,7 @@ static void integratorcm_write(void *opaque, hwaddr offset,
static const MemoryRegionOps integratorcm_ops = {
.read = integratorcm_read,
.write = integratorcm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void integratorcm_init(Object *obj)
@@ -439,7 +439,7 @@ static void icp_pic_write(void *opaque, hwaddr offset,
static const MemoryRegionOps icp_pic_ops = {
.read = icp_pic_read,
.write = icp_pic_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void icp_pic_init(Object *obj)
@@ -531,7 +531,7 @@ static void icp_control_write(void *opaque, hwaddr offset,
static const MemoryRegionOps icp_control_ops = {
.read = icp_control_read,
.write = icp_control_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void icp_control_mmc_wprot(void *opaque, int line, int level)
@@ -123,7 +123,7 @@ static void kzm_init(MachineState *machine)
if (serial_hd(2)) { /* touchscreen */
serial_mm_init(get_system_memory(), KZM_FPGA_ADDR+0x10, 0,
qdev_get_gpio_in(DEVICE(&s->soc.avic), 52),
- 14745600, serial_hd(2), DEVICE_NATIVE_ENDIAN);
+ 14745600, serial_hd(2), MO_TE);
}
kzm_binfo.ram_size = machine->ram_size;
@@ -141,7 +141,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
if (serial_hd(i)) {
serial_mm_init(get_system_memory(), uart_addr[i], 2,
qdev_get_gpio_in(armv7m, uart_irq[i]),
- 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
+ 115200, serial_hd(i), MO_TE);
}
}
@@ -371,7 +371,7 @@ static void mv88w8618_eth_write(void *opaque, hwaddr offset,
static const MemoryRegionOps mv88w8618_eth_ops = {
.read = mv88w8618_eth_read,
.write = mv88w8618_eth_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void eth_cleanup(NetClientState *nc)
@@ -617,7 +617,7 @@ static void musicpal_lcd_write(void *opaque, hwaddr offset,
static const MemoryRegionOps musicpal_lcd_ops = {
.read = musicpal_lcd_read,
.write = musicpal_lcd_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const GraphicHwOps musicpal_gfx_ops = {
@@ -758,7 +758,7 @@ static void mv88w8618_pic_reset(DeviceState *d)
static const MemoryRegionOps mv88w8618_pic_ops = {
.read = mv88w8618_pic_read,
.write = mv88w8618_pic_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void mv88w8618_pic_init(Object *obj)
@@ -922,7 +922,7 @@ static void mv88w8618_pit_reset(DeviceState *d)
static const MemoryRegionOps mv88w8618_pit_ops = {
.read = mv88w8618_pit_read,
.write = mv88w8618_pit_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void mv88w8618_pit_init(Object *obj)
@@ -1026,7 +1026,7 @@ static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset,
static const MemoryRegionOps mv88w8618_flashcfg_ops = {
.read = mv88w8618_flashcfg_read,
.write = mv88w8618_flashcfg_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void mv88w8618_flashcfg_init(Object *obj)
@@ -1099,7 +1099,7 @@ static void musicpal_misc_write(void *opaque, hwaddr offset,
static const MemoryRegionOps musicpal_misc_ops = {
.read = musicpal_misc_read,
.write = musicpal_misc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void musicpal_misc_init(Object *obj)
@@ -1147,7 +1147,7 @@ static void mv88w8618_wlan_write(void *opaque, hwaddr offset,
static const MemoryRegionOps mv88w8618_wlan_ops = {
.read = mv88w8618_wlan_read,
.write =mv88w8618_wlan_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void mv88w8618_wlan_realize(DeviceState *dev, Error **errp)
@@ -1344,7 +1344,7 @@ static void musicpal_gpio_write(void *opaque, hwaddr offset,
static const MemoryRegionOps musicpal_gpio_ops = {
.read = musicpal_gpio_read,
.write = musicpal_gpio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void musicpal_gpio_reset(DeviceState *d)
@@ -1614,11 +1614,11 @@ static void musicpal_init(MachineState *machine)
if (serial_hd(0)) {
serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
- 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ 1825000, serial_hd(0), MO_TE);
}
if (serial_hd(1)) {
serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
- 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
+ 1825000, serial_hd(1), MO_TE);
}
/* Register flash */
@@ -381,7 +381,7 @@ static void omap_wd_timer_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_wd_timer_ops = {
.read = omap_wd_timer_read,
.write = omap_wd_timer_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
@@ -493,7 +493,7 @@ static void omap_os_timer_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_os_timer_ops = {
.read = omap_os_timer_read,
.write = omap_os_timer_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
@@ -720,7 +720,7 @@ static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_ulpd_pm_ops = {
.read = omap_ulpd_pm_read,
.write = omap_ulpd_pm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
@@ -954,7 +954,7 @@ static void omap_pin_cfg_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_pin_cfg_ops = {
.read = omap_pin_cfg_read,
.write = omap_pin_cfg_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
@@ -1045,7 +1045,7 @@ static void omap_id_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_id_ops = {
.read = omap_id_read,
.write = omap_id_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
@@ -1134,7 +1134,7 @@ static void omap_mpui_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_mpui_ops = {
.read = omap_mpui_read,
.write = omap_mpui_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_mpui_reset(struct omap_mpu_state_s *s)
@@ -1237,7 +1237,7 @@ static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_tipb_bridge_ops = {
.read = omap_tipb_bridge_read,
.write = omap_tipb_bridge_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
@@ -1342,7 +1342,7 @@ static void omap_tcmi_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_tcmi_ops = {
.read = omap_tcmi_read,
.write = omap_tcmi_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
@@ -1437,7 +1437,7 @@ static void omap_dpll_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_dpll_ops = {
.read = omap_dpll_read,
.write = omap_dpll_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_dpll_reset(struct dpll_ctl_s *s)
@@ -1749,7 +1749,7 @@ static void omap_clkm_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_clkm_ops = {
.read = omap_clkm_read,
.write = omap_clkm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
@@ -1838,7 +1838,7 @@ static void omap_clkdsp_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_clkdsp_ops = {
.read = omap_clkdsp_read,
.write = omap_clkdsp_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_clkm_reset(struct omap_mpu_state_s *s)
@@ -2083,7 +2083,7 @@ static void omap_mpuio_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_mpuio_ops = {
.read = omap_mpuio_read,
.write = omap_mpuio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_mpuio_reset(struct omap_mpuio_s *s)
@@ -2289,7 +2289,7 @@ static void omap_uwire_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_uwire_ops = {
.read = omap_uwire_read,
.write = omap_uwire_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_uwire_reset(struct omap_uwire_s *s)
@@ -2400,7 +2400,7 @@ static void omap_pwl_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_pwl_ops = {
.read = omap_pwl_read,
.write = omap_pwl_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_pwl_reset(struct omap_pwl_s *s)
@@ -2518,7 +2518,7 @@ static void omap_pwt_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_pwt_ops = {
.read =omap_pwt_read,
.write = omap_pwt_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_pwt_reset(struct omap_pwt_s *s)
@@ -2855,7 +2855,7 @@ static void omap_rtc_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_rtc_ops = {
.read = omap_rtc_read,
.write = omap_rtc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_rtc_tick(void *opaque)
@@ -3453,7 +3453,7 @@ static void omap_mcbsp_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_mcbsp_ops = {
.read = omap_mcbsp_read,
.write = omap_mcbsp_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
@@ -3645,7 +3645,7 @@ static void omap_lpg_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_lpg_ops = {
.read = omap_lpg_read,
.write = omap_lpg_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_lpg_clk_update(void *opaque, int line, int on)
@@ -3698,7 +3698,7 @@ static void omap_mpui_io_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_mpui_io_ops = {
.read = omap_mpui_io_read,
.write = omap_mpui_io_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_setup_mpui_io(MemoryRegion *system_memory,
@@ -597,7 +597,7 @@ static void omap_eac_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_eac_ops = {
.read = omap_eac_read,
.write = omap_eac_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
@@ -748,7 +748,7 @@ static void omap_sti_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_sti_ops = {
.read = omap_sti_read,
.write = omap_sti_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
@@ -789,7 +789,7 @@ static void omap_sti_fifo_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_sti_fifo_ops = {
.read = omap_sti_fifo_read,
.write = omap_sti_fifo_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
@@ -1728,7 +1728,7 @@ static void omap_prcm_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_prcm_ops = {
.read = omap_prcm_read,
.write = omap_prcm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_prcm_reset(struct omap_prcm_s *s)
@@ -2128,7 +2128,7 @@ static const MemoryRegionOps omap_sysctl_ops = {
.write = omap_sysctl_writefn,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_sysctl_reset(struct omap_sysctl_s *s)
@@ -82,7 +82,7 @@ static void static_write(void *opaque, hwaddr offset,
static const MemoryRegionOps static_ops = {
.read = static_read,
.write = static_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
#define sdram_size 0x02000000
@@ -54,7 +54,7 @@ static const MemoryRegionOps static_ops = {
.write = static_write,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
/* Palm Tunsgten|E support */
@@ -152,7 +152,7 @@ static void pxa2xx_pm_write(void *opaque, hwaddr addr,
static const MemoryRegionOps pxa2xx_pm_ops = {
.read = pxa2xx_pm_read,
.write = pxa2xx_pm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_pxa2xx_pm = {
@@ -218,7 +218,7 @@ static void pxa2xx_cm_write(void *opaque, hwaddr addr,
static const MemoryRegionOps pxa2xx_cm_ops = {
.read = pxa2xx_cm_read,
.write = pxa2xx_cm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_pxa2xx_cm = {
@@ -442,7 +442,7 @@ static void pxa2xx_mm_write(void *opaque, hwaddr addr,
static const MemoryRegionOps pxa2xx_mm_ops = {
.read = pxa2xx_mm_read,
.write = pxa2xx_mm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_pxa2xx_mm = {
@@ -741,7 +741,7 @@ static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
static const MemoryRegionOps pxa2xx_ssp_ops = {
.read = pxa2xx_ssp_read,
.write = pxa2xx_ssp_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void pxa2xx_ssp_reset(DeviceState *d)
@@ -1108,7 +1108,7 @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
static const MemoryRegionOps pxa2xx_rtc_ops = {
.read = pxa2xx_rtc_read,
.write = pxa2xx_rtc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void pxa2xx_rtc_init(Object *obj)
@@ -1429,7 +1429,7 @@ static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
static const MemoryRegionOps pxa2xx_i2c_ops = {
.read = pxa2xx_i2c_read,
.write = pxa2xx_i2c_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
@@ -1687,7 +1687,7 @@ static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
static const MemoryRegionOps pxa2xx_i2s_ops = {
.read = pxa2xx_i2s_read,
.write = pxa2xx_i2s_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_pxa2xx_i2s = {
@@ -1924,7 +1924,7 @@ static void pxa2xx_fir_write(void *opaque, hwaddr addr,
static const MemoryRegionOps pxa2xx_fir_ops = {
.read = pxa2xx_fir_read,
.write = pxa2xx_fir_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static int pxa2xx_fir_is_empty(void *opaque)
@@ -2113,7 +2113,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
14857000 / 16, serial_hd(i),
- DEVICE_NATIVE_ENDIAN);
+ MO_TE);
} else {
break;
}
@@ -2237,7 +2237,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
14745600 / 16, serial_hd(i),
- DEVICE_NATIVE_ENDIAN);
+ MO_TE);
} else {
break;
}
@@ -259,7 +259,7 @@ static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
static const MemoryRegionOps pxa_gpio_ops = {
.read = pxa2xx_gpio_read,
.write = pxa2xx_gpio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
DeviceState *pxa2xx_gpio_init(hwaddr base,
@@ -256,7 +256,7 @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
static const MemoryRegionOps pxa2xx_pic_ops = {
.read = pxa2xx_pic_mem_read,
.write = pxa2xx_pic_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static int pxa2xx_pic_post_load(void *opaque, int version_id)
@@ -148,7 +148,7 @@ enum {
static const MemoryRegionOps sl_ops = {
.read = sl_read,
.write = sl_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void sl_flash_register(PXA2xxState *cpu, int size)
@@ -308,7 +308,7 @@ static void gptm_write(void *opaque, hwaddr offset,
static const MemoryRegionOps gptm_ops = {
.read = gptm_read,
.write = gptm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_stellaris_gptm = {
@@ -640,7 +640,7 @@ static void ssys_write(void *opaque, hwaddr offset,
static const MemoryRegionOps ssys_ops = {
.read = ssys_read,
.write = ssys_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void ssys_reset(void *opaque)
@@ -877,7 +877,7 @@ static void stellaris_i2c_reset(stellaris_i2c_state *s)
static const MemoryRegionOps stellaris_i2c_ops = {
.read = stellaris_i2c_read,
.write = stellaris_i2c_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_stellaris_i2c = {
@@ -1147,7 +1147,7 @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
static const MemoryRegionOps stellaris_adc_ops = {
.read = stellaris_adc_read,
.write = stellaris_adc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_stellaris_adc = {
@@ -182,7 +182,7 @@ static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
static const MemoryRegionOps strongarm_pic_ops = {
.read = strongarm_pic_mem_read,
.write = strongarm_pic_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void strongarm_pic_initfn(Object *obj)
@@ -382,7 +382,7 @@ static void strongarm_rtc_write(void *opaque, hwaddr addr,
static const MemoryRegionOps strongarm_rtc_ops = {
.read = strongarm_rtc_read,
.write = strongarm_rtc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void strongarm_rtc_init(Object *obj)
@@ -630,7 +630,7 @@ static void strongarm_gpio_write(void *opaque, hwaddr offset,
static const MemoryRegionOps strongarm_gpio_ops = {
.read = strongarm_gpio_read,
.write = strongarm_gpio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static DeviceState *strongarm_gpio_init(hwaddr base,
@@ -823,7 +823,7 @@ static void strongarm_ppc_write(void *opaque, hwaddr offset,
static const MemoryRegionOps strongarm_ppc_ops = {
.read = strongarm_ppc_read,
.write = strongarm_ppc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void strongarm_ppc_init(Object *obj)
@@ -1228,7 +1228,7 @@ static void strongarm_uart_write(void *opaque, hwaddr addr,
static const MemoryRegionOps strongarm_uart_ops = {
.read = strongarm_uart_read,
.write = strongarm_uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void strongarm_uart_init(Object *obj)
@@ -1517,7 +1517,7 @@ static void strongarm_ssp_write(void *opaque, hwaddr addr,
static const MemoryRegionOps strongarm_ssp_ops = {
.read = strongarm_ssp_read,
.write = strongarm_ssp_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static int strongarm_ssp_post_load(void *opaque, int version_id)
@@ -151,7 +151,7 @@ static void vpb_sic_write(void *opaque, hwaddr offset,
static const MemoryRegionOps vpb_sic_ops = {
.read = vpb_sic_read,
.write = vpb_sic_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void vpb_sic_init(Object *obj)
@@ -1069,7 +1069,7 @@ static const MemoryRegionOps intel_hda_mmio_ops = {
.min_access_size = 1,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
/* --------------------------------------------------------------------- */
@@ -984,13 +984,13 @@ static void fdctrl_write_mem (void *opaque, hwaddr reg,
static const MemoryRegionOps fdctrl_mem_ops = {
.read = fdctrl_read_mem,
.write = fdctrl_write_mem,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const MemoryRegionOps fdctrl_mem_strict_ops = {
.read = fdctrl_read_mem,
.write = fdctrl_write_mem,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
@@ -695,7 +695,7 @@ static MemTxResult pflash_mem_write_with_attrs(void *opaque, hwaddr addr, uint64
static const MemoryRegionOps pflash_cfi01_ops = {
.read_with_attrs = pflash_mem_read_with_attrs,
.write_with_attrs = pflash_mem_write_with_attrs,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
@@ -714,7 +714,7 @@ static const MemoryRegionOps pflash_cfi02_ops = {
.write = pflash_write,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
@@ -247,7 +247,7 @@ static void bcm2835_aux_receive(void *opaque, const uint8_t *buf, int size)
static const MemoryRegionOps bcm2835_aux_ops = {
.read = bcm2835_aux_read,
.write = bcm2835_aux_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
};
@@ -111,7 +111,7 @@ static const MemoryRegionOps uart_mmio_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static int uart_can_rx(void *opaque)
@@ -483,7 +483,7 @@ static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
static const MemoryRegionOps exynos4210_uart_ops = {
.read = exynos4210_uart_read,
.write = exynos4210_uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.max_access_size = 4,
.unaligned = false
@@ -287,7 +287,7 @@ static void mcf_uart_receive(void *opaque, const uint8_t *buf, int size)
static const MemoryRegionOps mcf_uart_ops = {
.read = mcf_uart_read,
.write = mcf_uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void mcf_uart_instance_init(Object *obj)
@@ -63,7 +63,7 @@ struct omap_uart_s *omap_uart_init(hwaddr base,
s->serial = serial_mm_init(get_system_memory(), base, 2, irq,
omap_clk_getrate(fclk)/16,
chr ?: qemu_chr_new(label, "null", NULL),
- DEVICE_NATIVE_ENDIAN);
+ MO_TE);
return s;
}
@@ -155,7 +155,7 @@ static void omap_uart_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_uart_ops = {
.read = omap_uart_read,
.write = omap_uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
@@ -183,5 +183,5 @@ void omap_uart_attach(struct omap_uart_s *s, Chardev *chr)
s->serial = serial_mm_init(get_system_memory(), s->base, 2, s->irq,
omap_clk_getrate(s->fclk) / 16,
chr ?: qemu_chr_new("null", "null", NULL),
- DEVICE_NATIVE_ENDIAN);
+ MO_TE);
}
@@ -591,7 +591,7 @@ static const MemoryRegionOps parallel_mm_ops = {
.write = parallel_mm_writefn,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
/* If fd is zero, it means that the parallel device uses the console */
@@ -368,7 +368,7 @@ static void sh_serial_event(void *opaque, int event)
static const MemoryRegionOps sh_serial_ops = {
.read = sh_serial_read,
.write = sh_serial_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
void sh_serial_init(MemoryRegion *sysmem,
@@ -189,7 +189,7 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
static const MemoryRegionOps stm32f2xx_usart_ops = {
.read = stm32f2xx_usart_read,
.write = stm32f2xx_usart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static Property stm32f2xx_usart_properties[] = {
@@ -169,7 +169,7 @@ uart_write(void *opaque, hwaddr addr,
static const MemoryRegionOps uart_ops = {
.read = uart_read,
.write = uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 4
@@ -49,7 +49,7 @@ static void empty_slot_write(void *opaque, hwaddr addr,
static const MemoryRegionOps empty_slot_ops = {
.read = empty_slot_read,
.write = empty_slot_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
void empty_slot_init(hwaddr addr, uint64_t slot_size)
@@ -83,7 +83,7 @@ nand_write(void *opaque, hwaddr addr, uint64_t value,
static const MemoryRegionOps nand_ops = {
.read = nand_read,
.write = nand_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
struct tempsensor_t
@@ -235,7 +235,7 @@ static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
static const MemoryRegionOps gpio_ops = {
.read = gpio_read,
.write = gpio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -344,7 +344,7 @@ static void bcm2835_fb_write(void *opaque, hwaddr offset, uint64_t value,
static const MemoryRegionOps bcm2835_fb_ops = {
.read = bcm2835_fb_read,
.write = bcm2835_fb_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
};
@@ -270,7 +270,7 @@ static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
static const MemoryRegionOps cg3_reg_ops = {
.read = cg3_reg_read,
.write = cg3_reg_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 4,
@@ -1821,7 +1821,7 @@ static const MemoryRegionOps exynos4210_fimd_mmio_ops = {
.max_access_size = 4,
.unaligned = false
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static int exynos4210_fimd_load(void *opaque, int version_id)
@@ -73,7 +73,7 @@ static void jazz_led_write(void *opaque, hwaddr addr,
static const MemoryRegionOps led_ops = {
.read = jazz_led_read,
.write = jazz_led_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl.min_access_size = 1,
.impl.max_access_size = 1,
};
@@ -435,7 +435,7 @@ static const MemoryRegionOps tmu2_mmio_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void milkymist_tmu2_reset(DeviceState *d)
@@ -271,7 +271,7 @@ static const MemoryRegionOps vgafb_mmio_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void milkymist_vgafb_reset(DeviceState *d)
@@ -247,7 +247,7 @@ static void omap_diss_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_diss_ops = {
.read = omap_diss_read,
.write = omap_diss_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static uint64_t omap_disc_read(void *opaque, hwaddr addr,
@@ -591,7 +591,7 @@ static void omap_disc_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_disc_ops = {
.read = omap_disc_read,
.write = omap_disc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_rfbi_transfer_stop(struct omap_dss_s *s)
@@ -867,7 +867,7 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_rfbi_ops = {
.read = omap_rfbi_read,
.write = omap_rfbi_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static uint64_t omap_venc_read(void *opaque, hwaddr addr,
@@ -990,7 +990,7 @@ static void omap_venc_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_venc_ops = {
.read = omap_venc_read,
.write = omap_venc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static uint64_t omap_im3_read(void *opaque, hwaddr addr,
@@ -1044,7 +1044,7 @@ static void omap_im3_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_im3_ops = {
.read = omap_im3_read,
.write = omap_im3_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
@@ -331,7 +331,7 @@ static void omap_lcdc_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_lcdc_ops = {
.read = omap_lcdc_read,
.write = omap_lcdc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
void omap_lcdc_reset(struct omap_lcd_panel_s *s)
@@ -569,7 +569,7 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
static const MemoryRegionOps pxa2xx_lcdc_ops = {
.read = pxa2xx_lcdc_read,
.write = pxa2xx_lcdc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
/* Load new palette for a given DMA channel, convert to internal format */
@@ -464,7 +464,7 @@ static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
static const MemoryRegionOps tcx_dac_ops = {
.read = tcx_dac_readl,
.write = tcx_dac_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -545,7 +545,7 @@ static void tcx_rstip_writel(void *opaque, hwaddr addr,
static const MemoryRegionOps tcx_stip_ops = {
.read = tcx_stip_readl,
.write = tcx_stip_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -555,7 +555,7 @@ static const MemoryRegionOps tcx_stip_ops = {
static const MemoryRegionOps tcx_rstip_ops = {
.read = tcx_stip_readl,
.write = tcx_rstip_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -637,7 +637,7 @@ static void tcx_rblit_writel(void *opaque, hwaddr addr,
static const MemoryRegionOps tcx_blit_ops = {
.read = tcx_blit_readl,
.write = tcx_blit_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -647,7 +647,7 @@ static const MemoryRegionOps tcx_blit_ops = {
static const MemoryRegionOps tcx_rblit_ops = {
.read = tcx_blit_readl,
.write = tcx_rblit_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -709,7 +709,7 @@ static void tcx_thc_writel(void *opaque, hwaddr addr,
static const MemoryRegionOps tcx_thc_ops = {
.read = tcx_thc_readl,
.write = tcx_thc_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -731,7 +731,7 @@ static void tcx_dummy_writel(void *opaque, hwaddr addr,
static const MemoryRegionOps tcx_dummy_ops = {
.read = tcx_dummy_readl,
.write = tcx_dummy_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -62,7 +62,7 @@ static const MemoryRegionOps vga_mm_ctrl_ops = {
.valid.max_access_size = 4,
.impl.min_access_size = 1,
.impl.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void vga_mm_init(ISAVGAMMState *s, hwaddr vram_base,
@@ -303,7 +303,7 @@ static void xlnx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value,
static const MemoryRegionOps audio_ops = {
.read = xlnx_dp_audio_read,
.write = xlnx_dp_audio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s,
@@ -878,7 +878,7 @@ static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value,
static const MemoryRegionOps dp_ops = {
.read = xlnx_dp_read,
.write = xlnx_dp_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -993,7 +993,7 @@ static uint64_t xlnx_dp_vblend_read(void *opaque, hwaddr offset,
static const MemoryRegionOps vblend_ops = {
.read = xlnx_dp_vblend_read,
.write = xlnx_dp_vblend_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -1106,7 +1106,7 @@ static uint64_t xlnx_dp_avbufm_read(void *opaque, hwaddr offset,
static const MemoryRegionOps avbufm_ops = {
.read = xlnx_dp_avbufm_read,
.write = xlnx_dp_avbufm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -476,7 +476,7 @@ static int i8257_phony_handler(void *opaque, int nchan, int dma_pos,
static const MemoryRegionOps channel_io_ops = {
.read = i8257_read_chan,
.write = i8257_write_chan,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
@@ -500,7 +500,7 @@ static const MemoryRegionPortio pageh_portio_list[] = {
static const MemoryRegionOps cont_io_ops = {
.read = i8257_read_cont,
.write = i8257_write_cont,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
@@ -1552,7 +1552,7 @@ static void omap_dma_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_dma_ops = {
.read = omap_dma_read,
.write = omap_dma_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_dma_request(void *opaque, int drq, int req)
@@ -2073,7 +2073,7 @@ static void omap_dma4_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_dma4_ops = {
.read = omap_dma4_read,
.write = omap_dma4_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
@@ -427,7 +427,7 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
static const MemoryRegionOps pxa2xx_dma_ops = {
.read = pxa2xx_dma_read,
.write = pxa2xx_dma_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void pxa2xx_dma_request(void *opaque, int req_num, int on)
@@ -388,7 +388,7 @@ static const MemoryRegionOps rc4030_ops = {
.write = rc4030_write,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void update_jazz_irq(rc4030State *s)
@@ -491,7 +491,7 @@ static const MemoryRegionOps jazzio_ops = {
.write = jazzio_write,
.impl.min_access_size = 2,
.impl.max_access_size = 2,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
@@ -515,7 +515,7 @@ static void axidma_write(void *opaque, hwaddr addr,
static const MemoryRegionOps axidma_ops = {
.read = axidma_read,
.write = axidma_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
@@ -554,7 +554,7 @@ static void xlnx_dpdma_write(void *opaque, hwaddr offset,
static const MemoryRegionOps dma_ops = {
.read = xlnx_dpdma_read,
.write = xlnx_dpdma_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -277,7 +277,7 @@ static void bcm2835_gpio_reset(DeviceState *dev)
static const MemoryRegionOps bcm2835_gpio_ops = {
.read = bcm2835_gpio_read,
.write = bcm2835_gpio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_bcm2835_gpio = {
@@ -270,7 +270,7 @@ static const MemoryRegionOps imx_gpio_ops = {
.write = imx_gpio_write,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_imx_gpio = {
@@ -178,7 +178,7 @@ static void omap_gpio_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_gpio_ops = {
.read = omap_gpio_read,
.write = omap_gpio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_gpio_reset(struct omap_gpio_s *s)
@@ -593,7 +593,7 @@ static const MemoryRegionOps omap2_gpio_module_ops = {
.write = omap2_gpio_module_writep,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_gpif_reset(DeviceState *dev)
@@ -676,7 +676,7 @@ static void omap2_gpif_top_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap2_gpif_top_ops = {
.read = omap2_gpif_top_read,
.write = omap2_gpif_top_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_gpio_init(Object *obj)
@@ -97,7 +97,7 @@ static const MemoryRegionOps puv3_gpio_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void puv3_gpio_realize(DeviceState *dev, Error **errp)
@@ -266,7 +266,7 @@ static void exynos4210_i2c_write(void *opaque, hwaddr offset,
static const MemoryRegionOps exynos4210_i2c_ops = {
.read = exynos4210_i2c_read,
.write = exynos4210_i2c_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription exynos4210_i2c_vmstate = {
@@ -470,7 +470,7 @@ static const MemoryRegionOps omap_i2c_ops = {
.write = omap_i2c_writefn,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_i2c_init(Object *obj)
@@ -335,7 +335,7 @@ static const MemoryRegionOps ppc4xx_i2c_ops = {
.valid.max_access_size = 4,
.impl.min_access_size = 1,
.impl.max_access_size = 1,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void ppc4xx_i2c_init(Object *o)
@@ -207,7 +207,7 @@ static void kvm_apic_mem_write(void *opaque, hwaddr addr,
static const MemoryRegionOps kvm_apic_io_ops = {
.read = kvm_apic_mem_read,
.write = kvm_apic_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void kvm_apic_reset(APICCommonState *s)
@@ -719,7 +719,7 @@ static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size)
static const MemoryRegionOps vapic_ops = {
.write = vapic_write,
.read = vapic_read,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void vapic_realize(DeviceState *dev, Error **errp)
@@ -2000,7 +2000,7 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
static const MemoryRegionOps ioport80_io_ops = {
.write = ioport80_write,
.read = ioport80_read,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
@@ -2010,7 +2010,7 @@ static const MemoryRegionOps ioport80_io_ops = {
static const MemoryRegionOps ioportF0_io_ops = {
.write = ioportF0_write,
.read = ioportF0_read,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
@@ -36,7 +36,7 @@ static void xen_apic_mem_write(void *opaque, hwaddr addr,
static const MemoryRegionOps xen_apic_io_ops = {
.read = xen_apic_mem_read,
.write = xen_apic_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void xen_apic_realize(DeviceState *dev, Error **errp)
@@ -427,7 +427,7 @@ static void platform_mmio_write(void *opaque, hwaddr addr,
static const MemoryRegionOps platform_mmio_handler = {
.read = &platform_mmio_read,
.write = &platform_mmio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void platform_mmio_setup(PCIXenPlatformState *d)
@@ -129,7 +129,7 @@ softusb_write(void *opaque, hwaddr addr, uint64_t value,
static const MemoryRegionOps softusb_mmio_ops = {
.read = softusb_read,
.write = softusb_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -459,7 +459,7 @@ static const MemoryRegionOps i8042_mmio_ops = {
.write = kbd_mm_writefn,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
@@ -287,7 +287,7 @@ static void pxa2xx_keypad_write(void *opaque, hwaddr offset,
static const MemoryRegionOps pxa2xx_keypad_ops = {
.read = pxa2xx_keypad_read,
.write = pxa2xx_keypad_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_pxa2xx_keypad = {
@@ -138,7 +138,7 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
static const MemoryRegionOps aw_a10_pic_ops = {
.read = aw_a10_pic_read,
.write = aw_a10_pic_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_aw_a10_pic = {
@@ -878,7 +878,7 @@ static const MemoryRegionOps apic_io_ops = {
.impl.max_access_size = 4,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void apic_realize(DeviceState *dev, Error **errp)
@@ -96,7 +96,7 @@ static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
static const MemoryRegionOps gicv3_its_trans_ops = {
.read_with_attrs = gicv3_its_trans_read,
.write_with_attrs = gicv3_its_trans_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops)
@@ -2337,7 +2337,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
static const MemoryRegionOps nvic_sysreg_ops = {
.read_with_attrs = nvic_sysreg_read,
.write_with_attrs = nvic_sysreg_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr,
@@ -2384,7 +2384,7 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr,
static const MemoryRegionOps nvic_sysreg_ns_ops = {
.read_with_attrs = nvic_sysreg_ns_read,
.write_with_attrs = nvic_sysreg_ns_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static MemTxResult nvic_systick_write(void *opaque, hwaddr addr,
@@ -2416,7 +2416,7 @@ static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
static const MemoryRegionOps nvic_systick_ops = {
.read_with_attrs = nvic_systick_read,
.write_with_attrs = nvic_systick_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static int nvic_post_load(void *opaque, int version_id)
@@ -170,7 +170,7 @@ static void bcm2835_ic_write(void *opaque, hwaddr offset, uint64_t val,
static const MemoryRegionOps bcm2835_ic_ops = {
.read = bcm2835_ic_read,
.write = bcm2835_ic_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
};
@@ -304,7 +304,7 @@ static void bcm2836_control_write(void *opaque, hwaddr offset,
static const MemoryRegionOps bcm2836_control_ops = {
.read = bcm2836_control_read,
.write = bcm2836_control_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
};
@@ -405,7 +405,7 @@ static void exynos4210_combiner_reset(DeviceState *d)
static const MemoryRegionOps exynos4210_combiner_ops = {
.read = exynos4210_combiner_read,
.write = exynos4210_combiner_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
/*
@@ -314,7 +314,7 @@ static void grlib_irqmp_write(void *opaque, hwaddr addr,
static const MemoryRegionOps grlib_irqmp_ops = {
.read = grlib_irqmp_read,
.write = grlib_irqmp_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -404,7 +404,7 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
static const MemoryRegionOps ioapic_io_ops = {
.read = ioapic_mem_read,
.write = ioapic_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void ioapic_machine_done_notify(Notifier *notifier, void *data)
@@ -386,7 +386,7 @@ static void gic_reset(void *opaque)
static const MemoryRegionOps gic_ops = {
.read = gic_read,
.write = gic_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
.max_access_size = 8,
},
@@ -331,7 +331,7 @@ static void omap_inth_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_inth_mem_ops = {
.read = omap_inth_read,
.write = omap_inth_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -607,7 +607,7 @@ static void omap2_inth_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap2_inth_mem_ops = {
.read = omap2_inth_read,
.write = omap2_inth_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -97,7 +97,7 @@ static void ompic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
static const MemoryRegionOps ompic_ops = {
.read = ompic_read,
.write = ompic_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
.max_access_size = 8,
},
@@ -289,7 +289,7 @@ static void sh_intc_write(void *opaque, hwaddr offset,
static const MemoryRegionOps sh_intc_ops = {
.read = sh_intc_read,
.write = sh_intc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
@@ -136,7 +136,7 @@ static void slavio_intctl_mem_writel(void *opaque, hwaddr addr,
static const MemoryRegionOps slavio_intctl_mem_ops = {
.read = slavio_intctl_mem_readl,
.write = slavio_intctl_mem_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -206,7 +206,7 @@ static void slavio_intctlm_mem_writel(void *opaque, hwaddr addr,
static const MemoryRegionOps slavio_intctlm_mem_ops = {
.read = slavio_intctlm_mem_readl,
.write = slavio_intctlm_mem_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -143,7 +143,7 @@ pic_write(void *opaque, hwaddr addr,
static const MemoryRegionOps pic_ops = {
.read = pic_read,
.write = pic_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4
@@ -526,7 +526,7 @@ static void tpci200_write_las3(void *opaque, hwaddr addr, uint64_t val,
static const MemoryRegionOps tpci200_cfg_ops = {
.read = tpci200_read_cfg,
.write = tpci200_write_cfg,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 4
@@ -540,7 +540,7 @@ static const MemoryRegionOps tpci200_cfg_ops = {
static const MemoryRegionOps tpci200_las0_ops = {
.read = tpci200_read_las0,
.write = tpci200_write_las0,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 2,
.max_access_size = 2
@@ -550,7 +550,7 @@ static const MemoryRegionOps tpci200_las0_ops = {
static const MemoryRegionOps tpci200_las1_ops = {
.read = tpci200_read_las1,
.write = tpci200_write_las1,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 2
@@ -560,7 +560,7 @@ static const MemoryRegionOps tpci200_las1_ops = {
static const MemoryRegionOps tpci200_las2_ops = {
.read = tpci200_read_las2,
.write = tpci200_write_las2,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 2
@@ -570,7 +570,7 @@ static const MemoryRegionOps tpci200_las2_ops = {
static const MemoryRegionOps tpci200_las3_ops = {
.read = tpci200_read_las3,
.write = tpci200_write_las3,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 1
@@ -551,7 +551,7 @@ static const MemoryRegionOps m5206_mbar_ops = {
.write = m5206_mbar_writefn,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
qemu_irq *mcf5206_init(MemoryRegion *sysmem, uint32_t base, M68kCPU *cpu)
@@ -141,7 +141,7 @@ static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
static const MemoryRegionOps m5208_timer_ops = {
.read = m5208_timer_read,
.write = m5208_timer_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
@@ -175,7 +175,7 @@ static void m5208_sys_write(void *opaque, hwaddr addr,
static const MemoryRegionOps m5208_sys_ops = {
.read = m5208_sys_read,
.write = m5208_sys_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
@@ -160,7 +160,7 @@ static void mcf_intc_reset(DeviceState *dev)
static const MemoryRegionOps mcf_intc_ops = {
.read = mcf_intc_read,
.write = mcf_intc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void mcf_intc_instance_init(Object *obj)
@@ -166,7 +166,7 @@ static void boston_lcd_write(void *opaque, hwaddr addr,
static const MemoryRegionOps boston_lcd_ops = {
.read = boston_lcd_read,
.write = boston_lcd_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
@@ -245,7 +245,7 @@ static void boston_platreg_write(void *opaque, hwaddr addr,
static const MemoryRegionOps boston_platreg_ops = {
.read = boston_platreg_read,
.write = boston_platreg_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const TypeInfo boston_device = {
@@ -505,7 +505,7 @@ static void boston_mach_init(MachineState *machine)
s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2,
get_cps_irq(&s->cps, 3), 10000000,
- serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ serial_hd(0), MO_TE);
lcd = g_new(MemoryRegion, 1);
memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8);
@@ -973,7 +973,7 @@ static uint64_t gt64120_readl(void *opaque,
static const MemoryRegionOps isd_mem_ops = {
.read = gt64120_readl,
.write = gt64120_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
@@ -84,7 +84,7 @@ static void rtc_write(void *opaque, hwaddr addr,
static const MemoryRegionOps rtc_ops = {
.read = rtc_read,
.write = rtc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
@@ -105,7 +105,7 @@ static void dma_dummy_write(void *opaque, hwaddr addr,
static const MemoryRegionOps dma_dummy_ops = {
.read = dma_dummy_read,
.write = dma_dummy_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
#define MAGNUM_BIOS_SIZE_MAX 0x7e000
@@ -320,12 +320,12 @@ static void mips_jazz_init(MachineState *machine,
if (serial_hd(0)) {
serial_mm_init(address_space, 0x80006000, 0,
qdev_get_gpio_in(rc4030, 8), 8000000/16,
- serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ serial_hd(0), MO_TE);
}
if (serial_hd(1)) {
serial_mm_init(address_space, 0x80007000, 0,
qdev_get_gpio_in(rc4030, 9), 8000000/16,
- serial_hd(1), DEVICE_NATIVE_ENDIAN);
+ serial_hd(1), MO_TE);
}
/* Parallel port */
@@ -531,7 +531,7 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
static const MemoryRegionOps malta_fpga_ops = {
.read = malta_fpga_read,
.write = malta_fpga_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void malta_fpga_reset(void *opaque)
@@ -592,7 +592,7 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
malta_fgpa_display_event, NULL, s, NULL, true);
s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
- 230400, uart_chr, DEVICE_NATIVE_ENDIAN);
+ 230400, uart_chr, MO_TE);
malta_fpga_reset(s);
qemu_register_reset(malta_fpga_reset, s);
@@ -72,7 +72,7 @@ static uint64_t mips_qemu_read (void *opaque, hwaddr addr,
static const MemoryRegionOps mips_qemu_ops = {
.read = mips_qemu_read,
.write = mips_qemu_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
typedef struct ResetData {
@@ -72,7 +72,7 @@ static void intdbg_control_write(void *opaque, hwaddr offset,
static const MemoryRegionOps intdbg_control_ops = {
.read = intdbg_control_read,
.write = intdbg_control_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void intdbg_control_init(Object *obj)
@@ -563,7 +563,7 @@ static void arm_sysctl_write(void *opaque, hwaddr offset,
static const MemoryRegionOps arm_sysctl_ops = {
.read = arm_sysctl_read,
.write = arm_sysctl_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void arm_sysctl_gpio_set(void *opaque, int line, int level)
@@ -108,7 +108,7 @@ static void aspeed_xdma_write(void *opaque, hwaddr addr, uint64_t val,
static const MemoryRegionOps aspeed_xdma_ops = {
.read = aspeed_xdma_read,
.write = aspeed_xdma_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
};
@@ -239,7 +239,7 @@ static void bcm2835_mbox_write(void *opaque, hwaddr offset,
static const MemoryRegionOps bcm2835_mbox_ops = {
.read = bcm2835_mbox_read,
.write = bcm2835_mbox_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
};
@@ -346,7 +346,7 @@ static void bcm2835_property_write(void *opaque, hwaddr offset,
static const MemoryRegionOps bcm2835_property_ops = {
.read = bcm2835_property_read,
.write = bcm2835_property_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
};
@@ -92,7 +92,7 @@ static void bcm2835_rng_write(void *opaque, hwaddr offset,
static const MemoryRegionOps bcm2835_rng_ops = {
.read = bcm2835_rng_read,
.write = bcm2835_rng_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_bcm2835_rng = {
@@ -231,7 +231,7 @@ static uint64_t ecc_mem_read(void *opaque, hwaddr addr,
static const MemoryRegionOps ecc_mem_ops = {
.read = ecc_mem_read,
.write = ecc_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -260,7 +260,7 @@ static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr,
static const MemoryRegionOps ecc_diag_mem_ops = {
.read = ecc_diag_mem_read,
.write = ecc_diag_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
@@ -295,7 +295,7 @@ static void edu_mmio_write(void *opaque, hwaddr addr, uint64_t val,
static const MemoryRegionOps edu_mmio_ops = {
.read = edu_mmio_read,
.write = edu_mmio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 8,
@@ -101,7 +101,7 @@ static void exynos4210_clk_write(void *opaque, hwaddr offset,
static const MemoryRegionOps exynos4210_clk_ops = {
.read = exynos4210_clk_read,
.write = exynos4210_clk_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -458,7 +458,7 @@ static void exynos4210_pmu_write(void *opaque, hwaddr offset,
static const MemoryRegionOps exynos4210_pmu_ops = {
.read = exynos4210_pmu_read,
.write = exynos4210_pmu_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -216,7 +216,7 @@ static void exynos4210_rng_write(void *opaque, hwaddr offset,
static const MemoryRegionOps exynos4210_rng_ops = {
.read = exynos4210_rng_read,
.write = exynos4210_rng_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void exynos4210_rng_reset(DeviceState *dev)
@@ -267,7 +267,7 @@ static void imx25_ccm_write(void *opaque, hwaddr offset, uint64_t value,
static const struct MemoryRegionOps imx25_ccm_ops = {
.read = imx25_ccm_read,
.write = imx25_ccm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
/*
* Our device would not work correctly if the guest was doing
@@ -37,7 +37,7 @@ static void imx2_wdt_write(void *opaque, hwaddr addr,
static const MemoryRegionOps imx2_wdt_ops = {
.read = imx2_wdt_read,
.write = imx2_wdt_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
/*
* Our device would not work correctly if the guest was doing
@@ -293,7 +293,7 @@ static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
static const struct MemoryRegionOps imx31_ccm_ops = {
.read = imx31_ccm_read,
.write = imx31_ccm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
/*
* Our device would not work correctly if the guest was doing
@@ -697,7 +697,7 @@ static void imx6_analog_write(void *opaque, hwaddr offset, uint64_t value,
static const struct MemoryRegionOps imx6_ccm_ops = {
.read = imx6_ccm_read,
.write = imx6_ccm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
/*
* Our device would not work correctly if the guest was doing
@@ -714,7 +714,7 @@ static const struct MemoryRegionOps imx6_ccm_ops = {
static const struct MemoryRegionOps imx6_analog_ops = {
.read = imx6_analog_read,
.write = imx6_analog_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
/*
* Our device would not work correctly if the guest was doing
@@ -263,7 +263,7 @@ static void imx6_src_write(void *opaque, hwaddr offset, uint64_t value,
static const struct MemoryRegionOps imx6_src_ops = {
.read = imx6_src_read,
.write = imx6_src_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
/*
* Our device would not work correctly if the guest was doing
@@ -802,7 +802,7 @@ static void imx6ul_analog_write(void *opaque, hwaddr offset, uint64_t value,
static const struct MemoryRegionOps imx6ul_ccm_ops = {
.read = imx6ul_ccm_read,
.write = imx6ul_ccm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
/*
* Our device would not work correctly if the guest was doing
@@ -819,7 +819,7 @@ static const struct MemoryRegionOps imx6ul_ccm_ops = {
static const struct MemoryRegionOps imx6ul_analog_ops = {
.read = imx6ul_analog_read,
.write = imx6ul_analog_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
/*
* Our device would not work correctly if the guest was doing
@@ -117,7 +117,7 @@ static void imx7_set_clr_tog_write(void *opaque, hwaddr offset,
static const struct MemoryRegionOps imx7_set_clr_tog_ops = {
.read = imx7_set_clr_tog_read,
.write = imx7_set_clr_tog_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
/*
* Our device would not work correctly if the guest was doing
@@ -133,7 +133,7 @@ static const struct MemoryRegionOps imx7_set_clr_tog_ops = {
static const struct MemoryRegionOps imx7_digprog_ops = {
.read = imx7_set_clr_tog_read,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
@@ -78,7 +78,7 @@ static void imx7_gpr_write(void *opaque, hwaddr offset,
static const struct MemoryRegionOps imx7_gpr_ops = {
.read = imx7_gpr_read,
.write = imx7_gpr_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
/*
* Our device would not work correctly if the guest was doing
@@ -37,7 +37,7 @@ static void imx7_snvs_write(void *opaque, hwaddr offset,
static const struct MemoryRegionOps imx7_snvs_ops = {
.read = imx7_snvs_read,
.write = imx7_snvs_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
/*
* Our device would not work correctly if the guest was doing
@@ -276,7 +276,7 @@ static uint64_t ivshmem_io_read(void *opaque, hwaddr addr,
static const MemoryRegionOps ivshmem_mmio_ops = {
.read = ivshmem_io_read,
.write = ivshmem_io_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
@@ -113,7 +113,7 @@ static const MemoryRegionOps hpdmc_mmio_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void milkymist_hpdmc_reset(DeviceState *d)
@@ -476,7 +476,7 @@ static const MemoryRegionOps pfpu_mmio_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void milkymist_pfpu_reset(DeviceState *d)
@@ -170,7 +170,7 @@ static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
static const MemoryRegionOps gcr_ops = {
.read = gcr_read,
.write = gcr_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
.max_access_size = 8,
},
@@ -113,7 +113,7 @@ static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size)
static const MemoryRegionOps cpc_ops = {
.read = cpc_read,
.write = cpc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
.max_access_size = 8,
},
@@ -142,7 +142,7 @@ static const MemoryRegionOps itc_tag_ops = {
.impl = {
.max_access_size = 8,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static inline uint32_t get_num_cells(MIPSITUState *s)
@@ -483,7 +483,7 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
static const MemoryRegionOps itc_storage_ops = {
.read = itc_storage_read,
.write = itc_storage_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void itc_reset_cells(MIPSITUState *s)
@@ -365,7 +365,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
static const MemoryRegionOps mos6522_ops = {
.read = mos6522_read,
.write = mos6522_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
@@ -96,7 +96,7 @@ static void msf2_sysreg_write(void *opaque, hwaddr offset,
static const MemoryRegionOps sysreg_ops = {
.read = msf2_sysreg_read,
.write = msf2_sysreg_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void msf2_sysreg_init(Object *obj)
@@ -192,7 +192,7 @@ mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
static const MemoryRegionOps mst_fpga_ops = {
.read = mst_fpga_readb,
.write = mst_fpga_writeb,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static int mst_fpga_post_load(void *opaque, int version_id)
@@ -213,7 +213,7 @@ static void omap_nand_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_nand_ops = {
.read = omap_nand_read,
.write = omap_nand_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void fill_prefetch_fifo(struct omap_gpmc_s *s)
@@ -370,7 +370,7 @@ static void omap_gpmc_prefetch_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_prefetch_ops = {
.read = omap_gpmc_prefetch_read,
.write = omap_gpmc_prefetch_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl.min_access_size = 1,
.impl.max_access_size = 1,
};
@@ -820,7 +820,7 @@ static void omap_gpmc_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_gpmc_ops = {
.read = omap_gpmc_read,
.write = omap_gpmc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
@@ -106,7 +106,7 @@ static void omap_l4ta_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_l4ta_ops = {
.read = omap_l4ta_read,
.write = omap_l4ta_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus,
@@ -151,7 +151,7 @@ static void omap_sdrc_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_sdrc_ops = {
.read = omap_sdrc_read,
.write = omap_sdrc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
@@ -106,7 +106,7 @@ static void omap_tap_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_tap_ops = {
.read = omap_tap_read,
.write = omap_tap_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
void omap_tap_init(struct omap_target_agent_s *ta,
@@ -144,7 +144,7 @@ static uint64_t slavio_cfg_mem_readb(void *opaque, hwaddr addr,
static const MemoryRegionOps slavio_cfg_mem_ops = {
.read = slavio_cfg_mem_readb,
.write = slavio_cfg_mem_writeb,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
@@ -174,7 +174,7 @@ static uint64_t slavio_diag_mem_readb(void *opaque, hwaddr addr,
static const MemoryRegionOps slavio_diag_mem_ops = {
.read = slavio_diag_mem_readb,
.write = slavio_diag_mem_writeb,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
@@ -204,7 +204,7 @@ static uint64_t slavio_mdm_mem_readb(void *opaque, hwaddr addr,
static const MemoryRegionOps slavio_mdm_mem_ops = {
.read = slavio_mdm_mem_readb,
.write = slavio_mdm_mem_writeb,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
@@ -242,7 +242,7 @@ static uint64_t slavio_aux1_mem_readb(void *opaque, hwaddr addr,
static const MemoryRegionOps slavio_aux1_mem_ops = {
.read = slavio_aux1_mem_readb,
.write = slavio_aux1_mem_writeb,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
@@ -279,7 +279,7 @@ static uint64_t slavio_aux2_mem_readb(void *opaque, hwaddr addr,
static const MemoryRegionOps slavio_aux2_mem_ops = {
.read = slavio_aux2_mem_readb,
.write = slavio_aux2_mem_writeb,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
@@ -307,7 +307,7 @@ static uint64_t apc_mem_readb(void *opaque, hwaddr addr,
static const MemoryRegionOps apc_mem_ops = {
.read = apc_mem_readb,
.write = apc_mem_writeb,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
@@ -352,7 +352,7 @@ static void slavio_sysctrl_mem_writel(void *opaque, hwaddr addr,
static const MemoryRegionOps slavio_sysctrl_mem_ops = {
.read = slavio_sysctrl_mem_readl,
.write = slavio_sysctrl_mem_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -394,7 +394,7 @@ static void slavio_led_mem_writew(void *opaque, hwaddr addr,
static const MemoryRegionOps slavio_led_mem_ops = {
.read = slavio_led_mem_readw,
.write = slavio_led_mem_writew,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 2,
.max_access_size = 2,
@@ -126,7 +126,7 @@ static void stm32f2xx_syscfg_write(void *opaque, hwaddr addr,
static const MemoryRegionOps stm32f2xx_syscfg_ops = {
.read = stm32f2xx_syscfg_read,
.write = stm32f2xx_syscfg_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void stm32f2xx_syscfg_init(Object *obj)
@@ -46,7 +46,7 @@ static const MemoryRegionOps unimp_ops = {
.impl.max_access_size = 8,
.valid.min_access_size = 1,
.valid.max_access_size = 8,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void unimp_realize(DeviceState *dev, Error **errp)
@@ -251,7 +251,7 @@ static void zynq_xadc_write(void *opaque, hwaddr offset, uint64_t val,
static const MemoryRegionOps xadc_ops = {
.read = zynq_xadc_read,
.write = zynq_xadc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void zynq_xadc_init(Object *obj)
@@ -415,7 +415,7 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
static const MemoryRegionOps slcr_ops = {
.read = zynq_slcr_read,
.write = zynq_slcr_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void zynq_slcr_init(Object *obj)
@@ -654,7 +654,7 @@ static const MemoryRegionOps dp8393x_ops = {
.write = dp8393x_write,
.impl.min_access_size = 2,
.impl.max_access_size = 2,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void dp8393x_watchdog(void *opaque)
@@ -283,7 +283,7 @@ static void etsec_write(void *opaque,
static const MemoryRegionOps etsec_ops = {
.read = etsec_read,
.write = etsec_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
@@ -626,7 +626,7 @@ static ssize_t mcf_fec_receive(NetClientState *nc, const uint8_t *buf, size_t si
static const MemoryRegionOps mcf_fec_ops = {
.read = mcf_fec_read,
.write = mcf_fec_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static NetClientInfo net_mcf_fec_info = {
@@ -433,7 +433,7 @@ static const MemoryRegionOps minimac2_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void milkymist_minimac2_reset(DeviceState *d)
@@ -168,7 +168,7 @@ eth_write(void *opaque, hwaddr addr,
static const MemoryRegionOps eth_ops = {
.read = eth_read,
.write = eth_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4
@@ -91,7 +91,7 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
/* Register: Altera 16550 UART */
serial_mm_init(address_space_mem, 0xf8001600, 2, irq[1], 115200,
- serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ serial_hd(0), MO_TE);
/* Register: Timer sys_clk_timer */
dev = qdev_create(NULL, "ALTR.timer");
@@ -166,7 +166,7 @@ static void openrisc_sim_init(MachineState *machine)
}
serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq,
- 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ 115200, serial_hd(0), MO_TE);
openrisc_load_kernel(ram_size, kernel_filename);
}
@@ -313,7 +313,7 @@ static uint64_t bonito_readl(void *opaque, hwaddr addr,
static const MemoryRegionOps bonito_ops = {
.read = bonito_readl,
.write = bonito_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -346,7 +346,7 @@ static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr,
static const MemoryRegionOps bonito_pciconf_ops = {
.read = bonito_pciconf_readl,
.write = bonito_pciconf_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -383,7 +383,7 @@ static void bonito_ldma_writel(void *opaque, hwaddr addr,
static const MemoryRegionOps bonito_ldma_ops = {
.read = bonito_ldma_readl,
.write = bonito_ldma_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -420,7 +420,7 @@ static void bonito_cop_writel(void *opaque, hwaddr addr,
static const MemoryRegionOps bonito_cop_ops = {
.read = bonito_cop_readl,
.write = bonito_cop_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -526,7 +526,7 @@ static const MemoryRegionOps bonito_spciconf_ops = {
.valid.max_access_size = 4,
.impl.min_access_size = 1,
.impl.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
#define BONITO_IRQ_BASE 32
@@ -117,19 +117,19 @@ static void pxa2xx_pcmcia_io_write(void *opaque, hwaddr offset,
static const MemoryRegionOps pxa2xx_pcmcia_common_ops = {
.read = pxa2xx_pcmcia_common_read,
.write = pxa2xx_pcmcia_common_write,
- .endianness = DEVICE_NATIVE_ENDIAN
+ .endianness = MO_TE
};
static const MemoryRegionOps pxa2xx_pcmcia_attr_ops = {
.read = pxa2xx_pcmcia_attr_read,
.write = pxa2xx_pcmcia_attr_write,
- .endianness = DEVICE_NATIVE_ENDIAN
+ .endianness = MO_TE
};
static const MemoryRegionOps pxa2xx_pcmcia_io_ops = {
.read = pxa2xx_pcmcia_io_read,
.write = pxa2xx_pcmcia_io_write,
- .endianness = DEVICE_NATIVE_ENDIAN
+ .endianness = MO_TE
};
static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level)
@@ -383,7 +383,7 @@ static const MemoryRegionOps taihu_cpld_ops = {
.min_access_size = 1,
.max_access_size = 1,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void taihu_cpld_reset (void *opaque)
@@ -724,7 +724,7 @@ static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value,
static const MemoryRegionOps ppc405_gpio_ops = {
.read = ppc405_gpio_read,
.write = ppc405_gpio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void ppc405_gpio_reset (void *opaque)
@@ -1106,7 +1106,7 @@ static const MemoryRegionOps gpt_ops = {
.write = ppc4xx_gpt_write,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void ppc4xx_gpt_cb (void *opaque)
@@ -75,7 +75,7 @@ static void sifive_prci_write(void *opaque, hwaddr addr,
static const MemoryRegionOps sifive_prci_ops = {
.read = sifive_prci_read,
.write = sifive_prci_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4
@@ -53,7 +53,7 @@ static void sifive_test_write(void *opaque, hwaddr addr,
static const MemoryRegionOps sifive_test_ops = {
.read = sifive_test_read,
.write = sifive_test_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4
@@ -134,7 +134,7 @@ uart_write(void *opaque, hwaddr addr,
static const MemoryRegionOps uart_ops = {
.read = uart_read,
.write = uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4
@@ -637,7 +637,7 @@ static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
static const MemoryRegionOps sysbus_esp_mem_ops = {
.read = sysbus_esp_mem_read,
.write = sysbus_esp_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid.accepts = esp_mem_accepts,
};
@@ -372,7 +372,7 @@ static void bcm2835_sdhost_write(void *opaque, hwaddr offset,
static const MemoryRegionOps bcm2835_sdhost_ops = {
.read = bcm2835_sdhost_read,
.write = bcm2835_sdhost_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static const VMStateDescription vmstate_bcm2835_sdhost = {
@@ -236,7 +236,7 @@ static const MemoryRegionOps memcard_mmio_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void milkymist_memcard_reset(DeviceState *d)
@@ -571,7 +571,7 @@ static void omap_mmc_write(void *opaque, hwaddr offset,
static const MemoryRegionOps omap_mmc_ops = {
.read = omap_mmc_read,
.write = omap_mmc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void omap_mmc_cover_cb(void *opaque, int line, int level)
@@ -472,7 +472,7 @@ static void pxa2xx_mmci_write(void *opaque,
static const MemoryRegionOps pxa2xx_mmci_ops = {
.read = pxa2xx_mmci_read,
.write = pxa2xx_mmci_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
@@ -179,7 +179,7 @@ static const MemoryRegionOps r2d_fpga_ops = {
.write = r2d_fpga_write,
.impl.min_access_size = 2,
.impl.max_access_size = 2,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
@@ -488,7 +488,7 @@ static const MemoryRegionOps sh7750_mem_ops = {
.write = sh7750_mem_writefn,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
/* sh775x interrupt controller tables for sh_intc.c
@@ -749,7 +749,7 @@ static void sh7750_mmct_write(void *opaque, hwaddr addr,
static const MemoryRegionOps sh7750_mmct_ops = {
.read = sh7750_mmct_read,
.write = sh7750_mmct_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
@@ -104,7 +104,7 @@ static uint64_t sh_pci_reg_read (void *p, hwaddr addr,
static const MemoryRegionOps sh_pci_reg_ops = {
.read = sh_pci_reg_read,
.write = sh_pci_reg_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -238,7 +238,7 @@ static void iommu_mem_write(void *opaque, hwaddr addr,
static const MemoryRegionOps iommu_mem_ops = {
.read = iommu_mem_read,
.write = iommu_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -252,7 +252,7 @@ static void power_mem_write(void *opaque, hwaddr addr,
static const MemoryRegionOps power_mem_ops = {
.read = power_mem_read,
.write = power_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -398,7 +398,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
static const struct MemoryRegionOps imx_spi_ops = {
.read = imx_spi_read,
.write = imx_spi_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
/*
* Our device would not work correctly if the guest was doing
@@ -344,7 +344,7 @@ static void omap_mcspi_write(void *opaque, hwaddr addr,
static const MemoryRegionOps omap_mcspi_ops = {
.read = omap_mcspi_read,
.write = omap_mcspi_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
@@ -315,7 +315,7 @@ done:
static const MemoryRegionOps spi_ops = {
.read = spi_read,
.write = spi_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4
@@ -181,7 +181,7 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
static const MemoryRegionOps a10_pit_ops = {
.read = a10_pit_read,
.write = a10_pit_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static Property a10_pit_properties[] = {
@@ -147,7 +147,7 @@ static void timer_write(void *opaque, hwaddr addr,
static const MemoryRegionOps timer_ops = {
.read = timer_read,
.write = timer_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 1,
.max_access_size = 4
@@ -122,7 +122,7 @@ static const MemoryRegionOps digic_timer_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void digic_timer_init(Object *obj)
@@ -1416,7 +1416,7 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
static const MemoryRegionOps exynos4210_mct_ops = {
.read = exynos4210_mct_read,
.write = exynos4210_mct_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
/* MCT init */
@@ -377,7 +377,7 @@ static void exynos4210_pwm_reset(DeviceState *d)
static const MemoryRegionOps exynos4210_pwm_ops = {
.read = exynos4210_pwm_read,
.write = exynos4210_pwm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
/*
@@ -545,7 +545,7 @@ static void exynos4210_rtc_reset(DeviceState *d)
static const MemoryRegionOps exynos4210_rtc_ops = {
.read = exynos4210_rtc_read,
.write = exynos4210_rtc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
/*
@@ -489,7 +489,7 @@ static const MemoryRegionOps omap_gp_timer_ops = {
.write = omap_gp_timer_writefn,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
@@ -93,7 +93,7 @@ static const MemoryRegionOps omap_synctimer_ops = {
.write = omap_synctimer_writefn,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
@@ -99,7 +99,7 @@ static const MemoryRegionOps puv3_ost_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void puv3_ost_tick(void *opaque)
@@ -401,7 +401,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
static const MemoryRegionOps pxa2xx_timer_ops = {
.read = pxa2xx_timer_read,
.write = pxa2xx_timer_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void pxa2xx_timer_tick(void *opaque)
@@ -303,7 +303,7 @@ static void tmu012_write(void *opaque, hwaddr offset,
static const MemoryRegionOps tmu012_ops = {
.read = tmu012_read,
.write = tmu012_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
void tmu012_init(MemoryRegion *sysmem, hwaddr base,
@@ -322,7 +322,7 @@ static void slavio_timer_mem_writel(void *opaque, hwaddr addr,
static const MemoryRegionOps slavio_timer_mem_ops = {
.read = slavio_timer_mem_readl,
.write = slavio_timer_mem_writel,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -189,7 +189,7 @@ timer_write(void *opaque, hwaddr addr,
static const MemoryRegionOps timer_ops = {
.read = timer_read,
.write = timer_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4
@@ -35,7 +35,7 @@ static void chipidea_write(void *opaque, hwaddr offset,
static const struct MemoryRegionOps chipidea_ops = {
.read = chipidea_read,
.write = chipidea_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
/*
* Our device would not work correctly if the guest was doing
@@ -76,7 +76,7 @@ static void chipidea_dc_write(void *opaque, hwaddr offset,
static const struct MemoryRegionOps chipidea_dc_ops = {
.read = chipidea_dc_read,
.write = chipidea_dc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.impl = {
/*
* Our device would not work correctly if the guest was doing
@@ -679,7 +679,7 @@ static const MemoryRegionOps tusb_async_ops = {
.write = tusb_async_writefn,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void tusb_otg_tick(void *opaque)
@@ -316,7 +316,7 @@ static void virtio_mmio_write(void *opaque, hwaddr offset, uint64_t value,
static const MemoryRegionOps virtio_mem_ops = {
.read = virtio_mmio_read,
.write = virtio_mmio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void virtio_mmio_update_irq(DeviceState *opaque, uint16_t vector)
@@ -437,7 +437,7 @@ static void xen_pt_bar_write(void *o, hwaddr addr, uint64_t val,
}
static const MemoryRegionOps ops = {
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.read = xen_pt_bar_read,
.write = xen_pt_bar_write,
};
@@ -507,7 +507,7 @@ static bool pci_msix_accepts(void *opaque, hwaddr addr,
static const MemoryRegionOps pci_msix_ops = {
.read = pci_msix_read,
.write = pci_msix_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -266,7 +266,7 @@ static void xtensa_mx_pic_ext_reg_write(void *opaque, hwaddr offset,
static const MemoryRegionOps xtensa_mx_pic_ops = {
.read = xtensa_mx_pic_ext_reg_read,
.write = xtensa_mx_pic_ext_reg_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
.valid = {
.unaligned = true,
},
@@ -121,7 +121,7 @@ static void xtfpga_fpga_write(void *opaque, hwaddr addr,
static const MemoryRegionOps xtfpga_fpga_ops = {
.read = xtfpga_fpga_read,
.write = xtfpga_fpga_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
@@ -216,7 +216,7 @@ static void xtfpga_io_write(void *opaque, hwaddr addr,
static const MemoryRegionOps xtfpga_io_ops = {
.read = xtfpga_io_read,
.write = xtfpga_io_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
@@ -315,7 +315,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
}
serial_mm_init(system_io, 0x0d050020, 2, extints[0],
- 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ 115200, serial_hd(0), MO_TE);
dinfo = drive_get(IF_PFLASH, 0, 0);
if (dinfo) {
@@ -51,7 +51,7 @@ static void unassigned_io_write(void *opaque, hwaddr addr, uint64_t val,
const MemoryRegionOps unassigned_io_ops = {
.read = unassigned_io_read,
.write = unassigned_io_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
void cpu_outb(uint32_t addr, uint8_t val)
@@ -1298,7 +1298,7 @@ static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
const MemoryRegionOps unassigned_mem_ops = {
.valid.accepts = unassigned_mem_accepts,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = MO_TE,
};
static uint64_t memory_region_ram_device_read(void *opaque,
@@ -3277,7 +3277,7 @@ MemOp devend_memop(enum device_endian end)
static MemOp conv[] = {
[DEVICE_LITTLE_ENDIAN] = MO_LE,
[DEVICE_BIG_ENDIAN] = MO_BE,
- [DEVICE_NATIVE_ENDIAN] = MO_TE,
+ [MO_TE] = MO_TE,
[DEVICE_HOST_ENDIAN] = 0,
};
switch (end) {
@@ -70,7 +70,7 @@ uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result,
- DEVICE_NATIVE_ENDIAN);
+ MO_TE);
}
uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL,
@@ -138,7 +138,7 @@ uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result,
- DEVICE_NATIVE_ENDIAN);
+ MO_TE);
}
uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL,
@@ -240,7 +240,7 @@ uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
- DEVICE_NATIVE_ENDIAN);
+ MO_TE);
}
uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
@@ -344,7 +344,7 @@ void glue(address_space_stl, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
{
glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs,
- result, DEVICE_NATIVE_ENDIAN);
+ result, MO_TE);
}
void glue(address_space_stl_le, SUFFIX)(ARG1_DECL,
@@ -440,7 +440,7 @@ void glue(address_space_stw, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
{
glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
- DEVICE_NATIVE_ENDIAN);
+ MO_TE);
}
void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
@@ -504,7 +504,7 @@ void glue(address_space_stq, SUFFIX)(ARG1_DECL,
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
{
glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result,
- DEVICE_NATIVE_ENDIAN);
+ MO_TE);
}
void glue(address_space_stq_le, SUFFIX)(ARG1_DECL,