| Message ID | a4004849c87990e5379acc5d60a52492385cd8e0.1683131359.git.oleksii.kurochko@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | enable MMU for RISC-V | expand |
On 03.05.2023 18:31, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/include/asm/config.h > +++ b/xen/arch/riscv/include/asm/config.h > @@ -4,6 +4,37 @@ > #include <xen/const.h> > #include <xen/page-size.h> > > +/* > + * RISC-V64 Layout: > + * > + * From the riscv-privileged doc: > + * When mapping between narrower and wider addresses, > + * RISC-V zero-extends a narrower physical address to a wider size. > + * The mapping between 64-bit virtual addresses and the 39-bit usable > + * address space of Sv39 is not based on zero-extension but instead > + * follows an entrenched convention that allows an OS to use one or > + * a few of the most-significant bits of a full-size (64-bit) virtual > + * address to quickly distinguish user and supervisor address regions. > + * > + * It means that: > + * top VA bits are simply ignored for the purpose of translating to PA. > + * > + * ============================================================================ > + * Start addr | End addr | Size | Slot |area description > + * ============================================================================ > + * FFFFFFFFC0000000 | FFFFFFFFC0200000 | 2 MB | L2 511 | Xen > + * FFFFFFFFC0200000 | FFFFFFFFC0600000 | 4 MB | L2 511 | FDT > + * FFFFFFFFC0600000 | FFFFFFFFC0800000 | 2 MB | L2 511 | Fixmap > + * ... | 1 GB | L2 510 | Unused > + * 0000003200000000 | 0000007f40000000 | 331 GB | L2 200-609 | Direct map I guess the upper value is 509 here? > + * ... | 1 GB | L2 199 | Unused > + * 0000003100000000 | 0000003140000000 | 3 GB | L2 196-198 | Frametable The two leftmost columns cover 1Gb only. > + * ... | 1 GB | L2 195 | Unused > + * 0000003080000000 | 00000030c0000000 | 1 GB | L2 194 | VMAP > + * .................. unused .................. > + * ============================================================================ > + */ Two more remarks: This map is, aiui, Sv39-specific. The quotation from the doc doesn't really imply that, so I'd suggest to add something to make this explicit. This might be as simple as a suitable #ifdef around or inside the comment (even inside I think it'll be easily understood what it means; see e.g. the CONFIG_BIGMEM conditional in x86'es table). The other oddity here is the sorting of entries: You sort downwards by L2 slot, but upwards within slot 511. Once suitably re-ordered it'll become apparent that there's another "unused" row missing (or perhaps even two). Jan
diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/asm/config.h index 763a922a04..73b86ce789 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -4,6 +4,37 @@ #include <xen/const.h> #include <xen/page-size.h> +/* + * RISC-V64 Layout: + * + * From the riscv-privileged doc: + * When mapping between narrower and wider addresses, + * RISC-V zero-extends a narrower physical address to a wider size. + * The mapping between 64-bit virtual addresses and the 39-bit usable + * address space of Sv39 is not based on zero-extension but instead + * follows an entrenched convention that allows an OS to use one or + * a few of the most-significant bits of a full-size (64-bit) virtual + * address to quickly distinguish user and supervisor address regions. + * + * It means that: + * top VA bits are simply ignored for the purpose of translating to PA. + * + * ============================================================================ + * Start addr | End addr | Size | Slot |area description + * ============================================================================ + * FFFFFFFFC0000000 | FFFFFFFFC0200000 | 2 MB | L2 511 | Xen + * FFFFFFFFC0200000 | FFFFFFFFC0600000 | 4 MB | L2 511 | FDT + * FFFFFFFFC0600000 | FFFFFFFFC0800000 | 2 MB | L2 511 | Fixmap + * ... | 1 GB | L2 510 | Unused + * 0000003200000000 | 0000007f40000000 | 331 GB | L2 200-609 | Direct map + * ... | 1 GB | L2 199 | Unused + * 0000003100000000 | 0000003140000000 | 3 GB | L2 196-198 | Frametable + * ... | 1 GB | L2 195 | Unused + * 0000003080000000 | 00000030c0000000 | 1 GB | L2 194 | VMAP + * .................. unused .................. + * ============================================================================ + */ + #if defined(CONFIG_RISCV_64) # define LONG_BYTEORDER 3 # define ELFSIZE 64
Also it was added explanation about ignoring of top VA bits Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> --- Changes in V6: - update comment above the RISCV-64 layout table - add Slot column to the table with RISCV-64 Layout - update RV-64 layout table. --- Changes in V5: * the patch was introduced in the current patch series. --- xen/arch/riscv/include/asm/config.h | 31 +++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)