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Signed-off-by: Jan Beulich --- v2: New. --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -744,6 +744,23 @@ void __init detect_zen2_null_seg_behavio } +static void __init noinline detect_bugs(const struct cpuinfo_x86 *c) +{ + /* + * Older AMD CPUs don't save/load FOP/FIP/FDP unless an FPU exception + * is pending. Xen works around this at (F)XRSTOR time. + */ + if (!cpu_has(c, X86_FEATURE_RSTR_FP_ERR_PTRS)) + setup_force_cpu_cap(X86_BUG_FPU_PTRS); + + /* + * AMD CPUs before Zen2 don't clear segment bases/limits when loading + * a NULL selector. + */ + if (!cpu_has_nscb) + setup_force_cpu_cap(X86_BUG_NULL_SEG); +} + static void cf_check init_amd(struct cpuinfo_x86 *c) { u32 l, h; @@ -781,13 +805,6 @@ static void init_amd(struct cpuinfo_x86 wrmsr_amd_safe(0xc001100d, l, h & ~1); } - /* - * Older AMD CPUs don't save/load FOP/FIP/FDP unless an FPU exception - * is pending. Xen works around this at (F)XRSTOR time. - */ - if (c == &boot_cpu_data && !cpu_has(c, X86_FEATURE_RSTR_FP_ERR_PTRS)) - setup_force_cpu_cap(X86_BUG_FPU_PTRS); - if (c->x86 == 0x0f || c->x86 == 0x11) /* Always dispatch serialising on this hardare. */ __set_bit(X86_FEATURE_LFENCE_DISPATCH, c->x86_capability); @@ -796,17 +813,13 @@ static void init_amd(struct cpuinfo_x86 amd_init_ssbd(c); - /* Probe for NSCB on Zen2 CPUs when not virtualised */ - if (!cpu_has_hypervisor && !cpu_has_nscb && c == &boot_cpu_data && - c->x86 == 0x17) - detect_zen2_null_seg_behaviour(); + if (c == &boot_cpu_data) { + /* Probe for NSCB on Zen2 CPUs when not virtualised */ + if (!cpu_has_hypervisor && !cpu_has_nscb && c->x86 == 0x17) + detect_zen2_null_seg_behaviour(); - /* - * AMD CPUs before Zen2 don't clear segment bases/limits when loading - * a NULL selector. - */ - if (c == &boot_cpu_data && !cpu_has_nscb) - setup_force_cpu_cap(X86_BUG_NULL_SEG); + detect_bugs(c); + } /* MFENCE stops RDTSC speculation */ if (!cpu_has_lfence_dispatch)