diff mbox series

[RFC,16/22] x86/PMUv4: support LBR_Frz and CTR_Frz

Message ID b0d40a19feee66f509ebabfc84d9166affae8fd4.1698261255.git.edwin.torok@cloud.com (mailing list archive)
State New, archived
Headers show
Series vPMU bugfixes and support for PMUv5 | expand

Commit Message

Edwin Torok Oct. 25, 2023, 7:29 p.m. UTC 
From: Edwin Török <edvin.torok@citrix.com>

The behaviour is changed from Legacy to Streamlined for the LBR and
PERFMON freeze bits.
See "17.4.7 Freezing LBR and Performance Counters on PMI".

Instead of clearing the freeze bits through DEBUGCTL they are now
cleared through MSR 0x390 like everything else.

Signed-off-by: Edwin Török <edvin.torok@citrix.com>
---
 xen/arch/x86/cpu/vpmu_intel.c | 7 +++++++
 1 file changed, 7 insertions(+)
diff mbox series

Patch

diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
index 82cd2656ea..923fe42a0b 100644
--- a/xen/arch/x86/cpu/vpmu_intel.c
+++ b/xen/arch/x86/cpu/vpmu_intel.c
@@ -952,6 +952,13 @@  const struct arch_vpmu_ops *__init core2_vpmu_init(void)
          */
         global_ovf_ctrl_mask &= ~(1ULL << 61);
 
+    if ( version >= 4)
+        /* On PMU version 4 bits 58 and 59 are defined in
+         * IA32_PERF_GLOBAL_STATUS_RESET (same MSR as IA32_PERF_GLOBAL_STATUS).
+         * Also allow clearing overflow for processor trace, even if we don't support it yet.
+         * */
+        global_ovf_ctrl_mask &= ~((3ULL << 58) | (1ULL << 55));
+
     regs_sz = (sizeof(struct xen_pmu_intel_ctxt) - regs_off) +
               sizeof(uint64_t) * fixed_pmc_cnt +
               sizeof(struct xen_pmu_cntr_pair) * arch_pmc_cnt;