| Message ID | b5466e495943210adc48c754df98862ae49ee489.1654612169.git-series.marmarek@invisiblethingslab.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Xue - console over USB 3 Debug Capability | expand |
On 07.06.2022 16:30, Marek Marczykowski-Górecki wrote: > --- a/docs/misc/xen-command-line.pandoc > +++ b/docs/misc/xen-command-line.pandoc > @@ -721,10 +721,15 @@ Available alternatives, with their meaning, are: > > ### dbgp > > `= ehci[ <integer> | @pci<bus>:<slot>.<func> ]` > +> `= xue[ <integer> | @pci<bus>:<slot>.<func> ]` > > Specify the USB controller to use, either by instance number (when going > over the PCI busses sequentially) or by PCI device (must be on segment 0). > > +Use `ehci` for EHCI debug port, use `xue` for XHCI debug capability. Ah, this answers one of my questions on patch 1. But I still think the option should appear here in patch 1, with this patch extending it (and its doc). > --- a/xen/drivers/char/xue.c > +++ b/xen/drivers/char/xue.c > @@ -204,6 +204,7 @@ struct xue { > void *xhc_mmio; > > int open; > + int xhc_num; /* look for n-th xhc */ unsigned int? > @@ -252,24 +253,34 @@ static int xue_init_xhc(struct xue *xue) > uint64_t bar1; > uint64_t devfn; > > - /* > - * Search PCI bus 0 for the xHC. All the host controllers supported so far > - * are part of the chipset and are on bus 0. > - */ > - for ( devfn = 0; devfn < 256; devfn++ ) { > - uint32_t dev = (devfn & 0xF8) >> 3; > - uint32_t fun = devfn & 0x07; > - pci_sbdf_t sbdf = PCI_SBDF(0, dev, fun); > - uint32_t hdr = pci_conf_read8(sbdf, PCI_HEADER_TYPE); > - > - if ( hdr == 0 || hdr == 0x80 ) > + if ( xue->sbdf.sbdf == 0 ) > + { > + /* > + * Search PCI bus 0 for the xHC. All the host controllers supported so far > + * are part of the chipset and are on bus 0. > + */ > + for ( devfn = 0; devfn < 256; devfn++ ) > { > - if ( (pci_conf_read32(sbdf, PCI_CLASS_REVISION) >> 8) == XUE_XHC_CLASSC ) > + uint32_t dev = (devfn & 0xF8) >> 3; > + uint32_t fun = devfn & 0x07; > + pci_sbdf_t sbdf = PCI_SBDF(0, dev, fun); > + uint32_t hdr = pci_conf_read8(sbdf, PCI_HEADER_TYPE); > + > + if ( hdr == 0 || hdr == 0x80 ) > { > - xue->sbdf = sbdf; > - break; > + if ( (pci_conf_read32(sbdf, PCI_CLASS_REVISION) >> 8) == XUE_XHC_CLASSC ) > + { > + if ( xue->xhc_num-- ) > + continue; > + xue->sbdf = sbdf; > + break; > + } > } > } > + } else { Nit: } else { Jan
diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index 881fe409ac76..37a564c2386f 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -721,10 +721,15 @@ Available alternatives, with their meaning, are: ### dbgp > `= ehci[ <integer> | @pci<bus>:<slot>.<func> ]` +> `= xue[ <integer> | @pci<bus>:<slot>.<func> ]` Specify the USB controller to use, either by instance number (when going over the PCI busses sequentially) or by PCI device (must be on segment 0). +Use `ehci` for EHCI debug port, use `xue` for XHCI debug capability. +Xue driver will wait indefinitely for the debug host to connect - make sure the +cable is connected. + ### debug_stack_lines > `= <integer>` diff --git a/xen/drivers/char/xue.c b/xen/drivers/char/xue.c index a9ba25d9d07e..b253426a95f8 100644 --- a/xen/drivers/char/xue.c +++ b/xen/drivers/char/xue.c @@ -204,6 +204,7 @@ struct xue { void *xhc_mmio; int open; + int xhc_num; /* look for n-th xhc */ }; static void xue_sys_pause(void) @@ -252,24 +253,34 @@ static int xue_init_xhc(struct xue *xue) uint64_t bar1; uint64_t devfn; - /* - * Search PCI bus 0 for the xHC. All the host controllers supported so far - * are part of the chipset and are on bus 0. - */ - for ( devfn = 0; devfn < 256; devfn++ ) { - uint32_t dev = (devfn & 0xF8) >> 3; - uint32_t fun = devfn & 0x07; - pci_sbdf_t sbdf = PCI_SBDF(0, dev, fun); - uint32_t hdr = pci_conf_read8(sbdf, PCI_HEADER_TYPE); - - if ( hdr == 0 || hdr == 0x80 ) + if ( xue->sbdf.sbdf == 0 ) + { + /* + * Search PCI bus 0 for the xHC. All the host controllers supported so far + * are part of the chipset and are on bus 0. + */ + for ( devfn = 0; devfn < 256; devfn++ ) { - if ( (pci_conf_read32(sbdf, PCI_CLASS_REVISION) >> 8) == XUE_XHC_CLASSC ) + uint32_t dev = (devfn & 0xF8) >> 3; + uint32_t fun = devfn & 0x07; + pci_sbdf_t sbdf = PCI_SBDF(0, dev, fun); + uint32_t hdr = pci_conf_read8(sbdf, PCI_HEADER_TYPE); + + if ( hdr == 0 || hdr == 0x80 ) { - xue->sbdf = sbdf; - break; + if ( (pci_conf_read32(sbdf, PCI_CLASS_REVISION) >> 8) == XUE_XHC_CLASSC ) + { + if ( xue->xhc_num-- ) + continue; + xue->sbdf = sbdf; + break; + } } } + } else { + /* Verify if selected device is really xHC */ + if ( (pci_conf_read32(xue->sbdf, PCI_CLASS_REVISION) >> 8) != XUE_XHC_CLASSC ) + xue->sbdf.sbdf = 0; } if ( !xue->sbdf.sbdf ) @@ -999,12 +1010,29 @@ void __init xue_uart_init(void) { struct xue_uart *uart = &xue_uart; struct xue *xue = &uart->xue; + const char *e; if ( strncmp(opt_dbgp, "xue", 3) ) return; memset(xue, 0, sizeof(*xue)); + if ( isdigit(opt_dbgp[3]) || !opt_dbgp[3] ) + { + if ( opt_dbgp[3] ) + xue->xhc_num = simple_strtoul(opt_dbgp + 3, &e, 10); + } + else if ( strncmp(opt_dbgp + 3, "@pci", 4) == 0 ) + { + unsigned int bus, slot, func; + + e = parse_pci(opt_dbgp + 7, NULL, &bus, &slot, &func); + if ( !e || *e ) + return; + + xue->sbdf = PCI_SBDF(0, bus, slot, func); + } + xue->dbc_ctx = &ctx; xue->dbc_erst = &erst; xue->dbc_ering.trb = evt_trb;
Handle parameters similar to dbgp=ehci. Implement this by not resettting xhc_cf8 again in xue_init_xhc(), but using a value found there if non-zero. Additionally, add xue->xhc_num to select n-th controller. Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com> --- docs/misc/xen-command-line.pandoc | 5 +++- xen/drivers/char/xue.c | 56 ++++++++++++++++++++++++-------- 2 files changed, 47 insertions(+), 14 deletions(-)