From patchwork Mon Mar 25 13:30:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pu Wen X-Patchwork-Id: 10869165 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C26F1390 for ; Mon, 25 Mar 2019 13:42:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5876529357 for ; Mon, 25 Mar 2019 13:42:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 56B802935D; Mon, 25 Mar 2019 13:42:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D566529434 for ; Mon, 25 Mar 2019 13:42:01 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1h8Ppa-0004Mx-Eu; Mon, 25 Mar 2019 13:40:02 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1h8Ppa-0004Ka-0Q for xen-devel@lists.xenproject.org; Mon, 25 Mar 2019 13:40:02 +0000 X-Inumbo-ID: 7afed567-4f03-11e9-bc90-bc764e045a96 Received: from spam2.hygon.cn (unknown [110.188.70.11]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 7afed567-4f03-11e9-bc90-bc764e045a96; Mon, 25 Mar 2019 13:40:00 +0000 (UTC) Received: from MK-FE.hygon.cn ([172.23.18.61]) by spam2.hygon.cn with ESMTP id x2PDUP9j015617; Mon, 25 Mar 2019 21:30:25 +0800 (GMT-8) (envelope-from puwen@hygon.cn) Received: from cncheex01.Hygon.cn ([172.23.18.10]) by MK-FE.hygon.cn with ESMTP id x2PDUH5m001756; Mon, 25 Mar 2019 21:30:18 +0800 (GMT-8) (envelope-from puwen@hygon.cn) Received: from pw-vbox.hygon.cn (172.23.18.44) by cncheex01.Hygon.cn (172.23.18.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1466.3; Mon, 25 Mar 2019 21:30:22 +0800 From: Pu Wen To: Date: Mon, 25 Mar 2019 21:30:15 +0800 Message-ID: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [172.23.18.44] X-ClientProxiedBy: cncheex02.Hygon.cn (172.23.18.12) To cncheex01.Hygon.cn (172.23.18.10) X-MAIL: spam2.hygon.cn x2PDUP9j015617 X-DNSRBL: Subject: [Xen-devel] [PATCH v3 03/14] x86/cpu/vpmu: Add Hygon Dhyana and AMD Zen support for vPMU X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , Suravee Suthikulpanit , Pu Wen , Jan Beulich , Andrew Cooper , Boris Ostrovsky , Brian Woods , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP As Hygon Dhyana CPU share similar PMU architecture with AMD family 17h one, so add Hygon Dhyana support in vpmu_arch_initialise() and vpmu_init() by sharing AMD code path. Split the common part in amd_vpmu_init() to a static function _vpmu_init(), making AMD and Hygon to call the shared function to initialize vPMU. As current vPMU still not support Zen(family 17h), add 0x17 support to amd_vpmu_init(). Also create a function hygon_vpmu_init() for Hygon vPMU initialization. Both of AMD 17h and Hygon 18h have the same performance event select and counter MSRs as AMD 15h has, so reuse the 15h definitions for them. Signed-off-by: Pu Wen --- xen/arch/x86/cpu/vpmu.c | 5 ++++ xen/arch/x86/cpu/vpmu_amd.c | 57 ++++++++++++++++++++++++++++++++------------- xen/include/asm-x86/vpmu.h | 1 + 3 files changed, 47 insertions(+), 16 deletions(-) diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c index 8f6daf1..93a27d8 100644 --- a/xen/arch/x86/cpu/vpmu.c +++ b/xen/arch/x86/cpu/vpmu.c @@ -456,6 +456,7 @@ static int vpmu_arch_initialise(struct vcpu *v) switch ( vendor ) { case X86_VENDOR_AMD: + case X86_VENDOR_HYGON: ret = svm_vpmu_initialise(v); break; @@ -876,6 +877,10 @@ static int __init vpmu_init(void) if ( amd_vpmu_init() ) vpmu_mode = XENPMU_MODE_OFF; break; + case X86_VENDOR_HYGON: + if ( hygon_vpmu_init() ) + vpmu_mode = XENPMU_MODE_OFF; + break; case X86_VENDOR_INTEL: if ( core2_vpmu_init() ) vpmu_mode = XENPMU_MODE_OFF; diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c index 5efc39b..3fc955f 100644 --- a/xen/arch/x86/cpu/vpmu_amd.c +++ b/xen/arch/x86/cpu/vpmu_amd.c @@ -538,13 +538,37 @@ int svm_vpmu_initialise(struct vcpu *v) return 0; } -int __init amd_vpmu_init(void) +static int _vpmu_init(void) { unsigned int i; + if ( sizeof(struct xen_pmu_data) + + 2 * sizeof(uint64_t) * num_counters > PAGE_SIZE ) + { + printk(XENLOG_WARNING + "VPMU: Register bank does not fit into VPMU shared page\n"); + counters = ctrls = NULL; + num_counters = 0; + return -ENOSPC; + } + + for ( i = 0; i < num_counters; i++ ) + { + rdmsrl(ctrls[i], ctrl_rsvd[i]); + ctrl_rsvd[i] &= CTRL_RSVD_MASK; + } + + regs_sz = 2 * sizeof(uint64_t) * num_counters; + + return 0; +} + +int __init amd_vpmu_init(void) +{ switch ( current_cpu_data.x86 ) { case 0x15: + case 0x17: num_counters = F15H_NUM_COUNTERS; counters = AMD_F15H_COUNTERS; ctrls = AMD_F15H_CTRLS; @@ -565,24 +589,25 @@ int __init amd_vpmu_init(void) return -EINVAL; } - if ( sizeof(struct xen_pmu_data) + - 2 * sizeof(uint64_t) * num_counters > PAGE_SIZE ) - { - printk(XENLOG_WARNING - "VPMU: Register bank does not fit into VPMU shared page\n"); - counters = ctrls = NULL; - num_counters = 0; - return -ENOSPC; - } + return _vpmu_init(); +} - for ( i = 0; i < num_counters; i++ ) +int __init hygon_vpmu_init(void) +{ + switch ( current_cpu_data.x86 ) { - rdmsrl(ctrls[i], ctrl_rsvd[i]); - ctrl_rsvd[i] &= CTRL_RSVD_MASK; + case 0x18: + num_counters = F15H_NUM_COUNTERS; + counters = AMD_F15H_COUNTERS; + ctrls = AMD_F15H_CTRLS; + k7_counters_mirrored = 1; + break; + default: + printk(XENLOG_WARNING "VPMU: Unsupported CPU family %#x\n", + current_cpu_data.x86); + return -EINVAL; } - regs_sz = 2 * sizeof(uint64_t) * num_counters; - - return 0; + return _vpmu_init(); } diff --git a/xen/include/asm-x86/vpmu.h b/xen/include/asm-x86/vpmu.h index 1287b9f..55f85ba 100644 --- a/xen/include/asm-x86/vpmu.h +++ b/xen/include/asm-x86/vpmu.h @@ -52,6 +52,7 @@ struct arch_vpmu_ops { int core2_vpmu_init(void); int vmx_vpmu_initialise(struct vcpu *); int amd_vpmu_init(void); +int hygon_vpmu_init(void); int svm_vpmu_initialise(struct vcpu *); struct vpmu_struct {