From patchwork Thu Aug 3 10:22:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13339678 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D92A5C04A94 for ; Thu, 3 Aug 2023 10:23:34 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.576181.902064 (Exim 4.92) (envelope-from ) id 1qRVUM-0005XO-1f; Thu, 03 Aug 2023 10:23:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 576181.902064; Thu, 03 Aug 2023 10:23:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qRVUL-0005Wh-P3; Thu, 03 Aug 2023 10:23:25 +0000 Received: by outflank-mailman (input) for mailman id 576181; Thu, 03 Aug 2023 10:23:23 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qRVUJ-0005QX-Lm for xen-devel@lists.xenproject.org; Thu, 03 Aug 2023 10:23:23 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id c587ec01-31e7-11ee-8613-37d641c3527e; Thu, 03 Aug 2023 12:23:21 +0200 (CEST) Received: from beta.station (net-188-218-251-179.cust.vodafonedsl.it [188.218.251.179]) by support.bugseng.com (Postfix) with ESMTPSA id 217904EE0741; Thu, 3 Aug 2023 12:23:21 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c587ec01-31e7-11ee-8613-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Simone Ballarin Subject: [XEN PATCH 03/13] xen/arm: address violations of MISRA C:2012 Rule 7.3 Date: Thu, 3 Aug 2023 12:22:18 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contain violations of MISRA C:2012 Rule 7.3 whose headline states: "The lowercase character 'l' shall not be used in a literal suffix". Use the "L" suffix instead of the "l" suffix, to avoid potential ambiguity. If the "u" suffix is used near "L", use the "U" suffix instead, for consistency. The changes in this patch are mechanical. Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Luca Fancellu Reviewed-by: Stefano Stabellini --- xen/arch/arm/include/asm/processor.h | 6 +++--- xen/arch/arm/vtimer.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/asm/processor.h index 7e42ff8811..8e02410465 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -521,9 +521,9 @@ extern register_t __cpu_logical_map[]; #define CNTKCTL_EL1_EL0PTEN (1u<<9) /* Expose phys timer registers to EL0 */ /* Timer control registers */ -#define CNTx_CTL_ENABLE (1ul<<0) /* Enable timer */ -#define CNTx_CTL_MASK (1ul<<1) /* Mask IRQ */ -#define CNTx_CTL_PENDING (1ul<<2) /* IRQ pending */ +#define CNTx_CTL_ENABLE (1UL<<0) /* Enable timer */ +#define CNTx_CTL_MASK (1UL<<1) /* Mask IRQ */ +#define CNTx_CTL_PENDING (1UL<<2) /* IRQ pending */ /* Timer frequency mask */ #define CNTFRQ_MASK GENMASK(31, 0) diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index 48f2daa907..c54360e202 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -206,7 +206,7 @@ static bool vtimer_cntp_tval(struct cpu_user_regs *regs, register_t *r, if ( read ) { - *r = (uint32_t)((v->arch.phys_timer.cval - cntpct) & 0xffffffffull); + *r = (uint32_t)((v->arch.phys_timer.cval - cntpct) & 0xffffffffULL); } else {