[for,4.21,v7,2/4] xen/riscv: drop CONFIG_RISCV_ISA_RV64G

Commit Message

Oleksii Kurochko Feb. 20, 2025, 5:44 p.m. UTC

'G' stands for "imafd_zicsr_zifencei".

Extensions 'f' and 'd' aren't really needed for Xen, and allowing floating
point registers to be used can lead to crashes.

Extensions 'i', 'm', 'a', 'zicsr', and 'zifencei' are necessary for the
operation of Xen, which is why they are used explicitly (unconditionally)
in -march.

Drop "Base ISA" choice from riscv/Kconfig as it is always empty.

Signed-off-by: Oleksii Kurochko <[e-mail]>
---
Changes in V7:
 - For better readability use += instead of := for riscv-march-* in arch.mk.
 - Drop spaces from riscv-march-y by usage of subst macros.
 - Drop "Base ISA" choice as it is empty now.
 - Update the commit message.
---
Changes in V6:
 - new patch.
---
 xen/arch/riscv/Kconfig | 18 ------------------
 xen/arch/riscv/arch.mk |  8 +++++---
 2 files changed, 5 insertions(+), 21 deletions(-)

Patch

diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig
index fa95cd0a42..d882e0a059 100644
--- a/xen/arch/riscv/Kconfig
+++ b/xen/arch/riscv/Kconfig
@@ -23,24 +23,6 @@  endmenu
 
 menu "ISA Selection"
 
-choice
-	prompt "Base ISA"
-	default RISCV_ISA_RV64G if RISCV_64
-	help
-	  This selects the base ISA extensions that Xen will target.
-
-config RISCV_ISA_RV64G
-	bool "RV64G"
-	help
-	  Use the RV64I base ISA, plus
-	  "M" for multiply/divide,
-	  "A" for atomic instructions,
-	  “F”/"D" for  {single/double}-precision floating-point instructions,
-	  "Zicsr" for control and status register access,
-	  "Zifencei" for instruction-fetch fence.
-
-endchoice
-
 config RISCV_ISA_C
 	bool "Compressed extension"
 	default y
diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk
index 17827c302c..3034da76cb 100644
--- a/xen/arch/riscv/arch.mk
+++ b/xen/arch/riscv/arch.mk
@@ -6,10 +6,12 @@  $(call cc-options-add,CFLAGS,CC,$(EMBEDDED_EXTRA_CFLAGS))
 riscv-abi-$(CONFIG_RISCV_32) := -mabi=ilp32
 riscv-abi-$(CONFIG_RISCV_64) := -mabi=lp64
 
-riscv-march-$(CONFIG_RISCV_ISA_RV64G) := rv64g
-riscv-march-$(CONFIG_RISCV_ISA_C)       := $(riscv-march-y)c
+riscv-march-$(CONFIG_RISCV_64) := rv64
+riscv-march-y += ima
+riscv-march-$(CONFIG_RISCV_ISA_C) += c
+riscv-march-y += _zicsr_zifencei
 
-riscv-generic-flags := $(riscv-abi-y) -march=$(riscv-march-y)
+riscv-generic-flags := $(riscv-abi-y) -march=$(subst $(space),,$(riscv-march-y))
 
 # check-extension: Check whether extenstion is supported by a compiler and
 #                  an assembler.