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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id g29-20020a05651c079d00b002d0acb57c89sm568939lje.64.2024.03.15.11.06.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Mar 2024 11:06:22 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bbfdf0a6-e2f6-11ee-afdd-a90da7624cb6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1710525982; x=1711130782; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q3qDdX1fVf6ELC4xrUOmJazs4+QxaTvpRVXWbmDV/+I=; b=c244gl9HMfi2AY0bRn4d9pTaDtknWsPEtcrkhQO7Kxu4V1P+rXA2Zo6TZBzhJ3SG68 4NW8LNFwV/GedA4gAoRHVeI3aDWoGFtw14lmUvMnCTiYQNa+TmMvj9dthMPCOtUMZV4S UHZ0BdWnDlyxkUNr4xuNQdUgHRw5PPolB58ohR226T6r5XKNGQB9i4MX00dzlbn+qkkf x6Ymk52t6l+ps3IEKUZ2jp0TZXlF1EIQET0fPzPViL0ZSLkb4UqQYIiwJ3gyhu3KcMoC w2PjbJfgiONwQLejK9iUqlr2dhWSirRHJDrhljrEqPs7NBCLPPlTZkld1rQJiAYidZOy nwvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710525982; x=1711130782; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q3qDdX1fVf6ELC4xrUOmJazs4+QxaTvpRVXWbmDV/+I=; b=I1B5jhDOCDIYJQKvOrqM0grPJJm+qGaQCEB1yTiZFL/pXbjreHJumNmL1CK3CuwYGv Bc6d9HqKoHb2nZdBKPM3VMDpSp1FGLuFhzt9Ykwzk+FblInoP/ggkVDfxZ5Pc1HUe6JZ H8CJKSYdndqyKCu9go7xjUNhRDEwOs+mP8HeumqWckxGtYzjY8V1bYEKlxy6/5FJqjjD NDCVSQ9O9M9VCS2LlTLwX72H0VjC/tvkVbT+PzHGKP9H4nqFVgplD1l6vIq93dkDVH2Y CmLE2ujjtrIBunBAmVDTBQQkbUfdQ7IvOZjraqx44RMMEdsJZHkRxV7IDyeVAbTsH4yG RNNA== X-Gm-Message-State: AOJu0YwB3ctPuurQy88X9kWi4leseTDNgRZRlf+N7cPODKjkXo3JU7pW 5V6qoszLMyiRNGXWJERq02c1TzsPxKrUEqX8io6NCqAOSUfYRJM+oSgtxBkxMIQ= X-Google-Smtp-Source: AGHT+IHeNIXc4RZKYxoGE93x76137GYbYkx6boDJJaNuddaxGW6N1RgI0MJTtn6sDj0oCFFiEOV5OQ== X-Received: by 2002:a2e:be8f:0:b0:2d3:ba98:473 with SMTP id a15-20020a2ebe8f000000b002d3ba980473mr3172986ljr.19.1710525982507; Fri, 15 Mar 2024 11:06:22 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu , Alistair Francis , Bob Eshleman , Connor Davis Subject: [PATCH v6 03/20] xen/riscv: introduce extenstion support check by compiler Date: Fri, 15 Mar 2024 19:05:59 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Currently, RISC-V requires two extensions: _zbb and _zihintpause. This patch introduces a compiler check to check if these extensions are supported. Additionally, it introduces the riscv/booting.txt file, which contains information about the extensions that should be supported by the platform. In the future, a feature will be introduced to check whether an extension is supported at runtime. However, this feature requires functionality for parsing device tree source (DTS), which is not yet available. Signed-off-by: Oleksii Kurochko --- Changes in V6: - new patch for this patch series --- docs/misc/riscv/booting.txt | 16 ++++++++++++++++ xen/arch/riscv/arch.mk | 10 ++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) create mode 100644 docs/misc/riscv/booting.txt diff --git a/docs/misc/riscv/booting.txt b/docs/misc/riscv/booting.txt new file mode 100644 index 0000000000..cb4d79f12c --- /dev/null +++ b/docs/misc/riscv/booting.txt @@ -0,0 +1,16 @@ +System requirements +=================== + +The following extensions are expected to be supported by a system on which +Xen is run: +- Zbb: + RISC-V doesn't have a CLZ instruction in the base ISA. + As a consequence, __builtin_ffs() emits a library call to ffs() on GCC, + or a de Bruijn sequence on Clang. + Zbb extension adds a CLZ instruction, after which __builtin_ffs() emits + a very simple sequence. + The similar issue occurs with other __builtin_, so it is needed to + provide a generic version of bitops in RISC-V bitops.h +- Zihintpause: + On a system that doesn't have this extension, cpu_relax() should be + implemented properly. diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index 8403f96b6f..da6f8c82eb 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -3,16 +3,22 @@ $(call cc-options-add,CFLAGS,CC,$(EMBEDDED_EXTRA_CFLAGS)) -CFLAGS-$(CONFIG_RISCV_64) += -mabi=lp64 +riscv-abi-$(CONFIG_RISCV_32) := -mabi=ilp32 +riscv-abi-$(CONFIG_RISCV_64) := -mabi=lp64 riscv-march-$(CONFIG_RISCV_ISA_RV64G) := rv64g riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c +extensions := $(call as-insn,$(CC) $(riscv-abi-y) -march=$(riscv-march-y)_zbb,"",_zbb) \ + $(call as-insn,$(CC) $(riscv-abi-y) -march=$(riscv-march-y)_zihintpause,"pause",_zihintpause) + +extensions := $(subst $(space),,$(extensions)) + # Note that -mcmodel=medany is used so that Xen can be mapped # into the upper half _or_ the lower half of the address space. # -mcmodel=medlow would force Xen into the lower half. -CFLAGS += -march=$(riscv-march-y) -mstrict-align -mcmodel=medany +CFLAGS += $(riscv-abi-y) -march=$(riscv-march-y)$(extensions) -mstrict-align -mcmodel=medany # TODO: Drop override when more of the build is working override ALL_OBJS-y = arch/$(SRCARCH)/built_in.o