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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?zUhguwvVvRQdglLdR28cTzDxpeu9?= =?utf-8?q?EkVQFSg+BJtlrvWcSk2qqWX5JoR2+Z18OB+aT6HLQYd4BmH/6QI3oB5vmsz0NcfIy?= =?utf-8?q?hsGC/hOGkZqGfquPCr/gCFT484w8973XZDOiCrihkgVgeO4VwSaoKpCIwECvaud29?= =?utf-8?q?nX6K2VJNmFoC+yIyfurv/KH3Ol8Rb5Wspa7/BzmDbieRvBP0PQe3ZtP9QpQ+F9WZL?= =?utf-8?q?xUFo8mfp4irYCZY5cLrs2yNTEHFWtTF0fTE7NAWeBgFdhAeaKBXw6YexQmo9g8cSM?= =?utf-8?q?h/R6fo2xXcsHGSZTPP/aa90dLRuAFfYtZDczmR8cYVL/KAW8kLKqbAO4HwcmKMtGA?= =?utf-8?q?eyc/+wqD5viIHtXr2tHkc6dNOJ3yBOxg0Ms+rWdquWd3dMCOTNLi28SK/IpDvwHga?= =?utf-8?q?bg6U4dw28UgVPigtLcuHAM56usQoKZYeD58lginCQ/o9ocO+CfW9pT6yV+icPq9ta?= =?utf-8?q?pk8ul/x6GXEvtOjl+dhrD4SNr6vZnVav8/SpTr6MjwT+69KmcMvtSbktFtKccc01f?= =?utf-8?q?c8Ko0ohJRXH5Xz4nJ8TL6wL1wMbGbbtLHvpkx4HpkeWmTBbNsRjpKRjY2Tdk7UEbh?= =?utf-8?q?edR5UW1I96N/0NOclNgtx43jTSyJx/gL6xrreHUKsUQNioVDlZEELw3G0IgUFeO+F?= =?utf-8?q?vd7C9fMkNj1ds5SWBU+rGta0VLQP36qWfpZibDx4RRXrqupGTZqPUun0Uvv5eP7TX?= =?utf-8?q?Q2zyYwmpTAwRymuE4+/WEASz2wZAGL4wq4PRMgIEHhGff11TxEJA2lhdYdd8+YUub?= =?utf-8?q?OzNDJlA6oMXowG7IM5ycIw0AhiYXYbSudzZ2ef6mgvf3HMnQUgN6kFY8GSkzoiwQN?= =?utf-8?q?mW8/c/aRHnIzl3X92v42yQXyK1EbzB1nLcmX70kGx71zm23djVdaYKFp/ijmb70n0?= =?utf-8?q?dkukBA96M0aYpiNNj34LYQeJjUjXGRrMWm/2G1JISnIDdDBsO2TBZQeAKZWXAfNMy?= =?utf-8?q?tvJBiPiEyqNvhuMaHWd73V+dE10VXU8NDKIR2OA5f2V5cwFTwm2JZv1ik+1KbXc+U?= =?utf-8?q?PPqDbfeWV50XG7o1FBmtI1DCuMlt/yW3zWBUUmPI/2k04IshqfiJISHq/tPiBY/YN?= =?utf-8?q?5TF4I9xIBumVcIQ0+Nd53E1BNCQv50Rv1CQtPpX6iFfqgHXcaLnlOLubIwaMVrjeo?= =?utf-8?q?884kW/GGGuwWwEmSssPA5EmNiDFQYQsyr+WX1L3zf5UrIRK6DyYCnVuRAaCPtmgzd?= =?utf-8?q?yjfH1zWS0tcS7A9KNpG7uRLIm193859k7NzrqCHUpsGINrDBDDojMjr6WWd24y8ji?= =?utf-8?q?tejuReeeZntw2g2/65fHxthgzShIskrFyot9DcGiP3bh2RdlPX6c5NdyaaWtWTnXx?= =?utf-8?q?Zn7WVpyU3QQ6Hhsm9fTANQM9NpnMBKfZCLpJbfbYKVObVDatM78pc1Nx9NQQI3kRo?= =?utf-8?q?kWhiRdT2uYnNsXPqq1/qwddClvjSxIgxf5U12exT1maCizB01zFw5xCFjzZDEjWg+?= =?utf-8?q?ePGApDw6hLrKh/yk+p7mUPr5AKxqYbipSPzUD6/R5FjS+PUlQbKhlKJ5xa+LplU1c?= =?utf-8?q?nirugcBM7/aOKnlEVUW2Ydr/Lu0mpwU4TAwEg4mRA1rdnAy6TQ7FeT8=3D?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1b9d5ddd-7e77-4c67-b398-08d9b4ae9ab2 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5600.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2021 09:40:26.3696 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6Wz+LTp+1WdQ0+SraFh5OHLf18oPjNnt9Vaor7etwSnEJuGV0wXLXc/wAXkC1yrmCEBhEjobtlrO1CpzLCqMJQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB3293 The actual function should always have lived in core x86 code; move it there, replacing get_cache_line_size() by readily available (except very early during boot; see the code comment) data. Drop the respective IOMMU hook, (re)introducing a respective boolean instead. Replace a true and an almost open-coding instance of iommu_sync_cache(). Signed-off-by: Jan Beulich --- Placing the function next to flush_area_local() exposes a curious asymmetry between the SFENCE placements: sync_cache() has it after the flush, while flush_area_local() has it before it. I think the latter one is misplaced. --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -265,6 +266,57 @@ unsigned int flush_area_local(const void return flags; } +void sync_cache(const void *addr, unsigned int size) +{ + /* + * This function may be called before current_cpu_data is established. + * Hence a fallback is needed to prevent the loop below becoming infinite. + */ + unsigned int clflush_size = current_cpu_data.x86_clflush_size ?: 16; + const void *end = addr + size; + + addr -= (unsigned long)addr & (clflush_size - 1); + for ( ; addr < end; addr += clflush_size ) + { +/* + * The arguments to a macro must not include preprocessor directives. Doing so + * results in undefined behavior, so we have to create some defines here in + * order to avoid it. + */ +#if defined(HAVE_AS_CLWB) +# define CLWB_ENCODING "clwb %[p]" +#elif defined(HAVE_AS_XSAVEOPT) +# define CLWB_ENCODING "data16 xsaveopt %[p]" /* clwb */ +#else +# define CLWB_ENCODING ".byte 0x66, 0x0f, 0xae, 0x30" /* clwb (%%rax) */ +#endif + +#define BASE_INPUT(addr) [p] "m" (*(const char *)(addr)) +#if defined(HAVE_AS_CLWB) || defined(HAVE_AS_XSAVEOPT) +# define INPUT BASE_INPUT +#else +# define INPUT(addr) "a" (addr), BASE_INPUT(addr) +#endif + /* + * Note regarding the use of NOP_DS_PREFIX: it's faster to do a clflush + * + prefix than a clflush + nop, and hence the prefix is added instead + * of letting the alternative framework fill the gap by appending nops. + */ + alternative_io_2(".byte " __stringify(NOP_DS_PREFIX) "; clflush %[p]", + "data16 clflush %[p]", /* clflushopt */ + X86_FEATURE_CLFLUSHOPT, + CLWB_ENCODING, + X86_FEATURE_CLWB, /* no outputs */, + INPUT(addr)); +#undef INPUT +#undef BASE_INPUT +#undef CLWB_ENCODING + } + + alternative_2("", "sfence", X86_FEATURE_CLFLUSHOPT, + "sfence", X86_FEATURE_CLWB); +} + unsigned int guest_flush_tlb_flags(const struct domain *d) { bool shadow = paging_mode_shadow(d); --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -202,54 +202,6 @@ static void check_cleanup_domid_map(stru } } -static void sync_cache(const void *addr, unsigned int size) -{ - static unsigned long clflush_size = 0; - const void *end = addr + size; - - if ( clflush_size == 0 ) - clflush_size = get_cache_line_size(); - - addr -= (unsigned long)addr & (clflush_size - 1); - for ( ; addr < end; addr += clflush_size ) -/* - * The arguments to a macro must not include preprocessor directives. Doing so - * results in undefined behavior, so we have to create some defines here in - * order to avoid it. - */ -#if defined(HAVE_AS_CLWB) -# define CLWB_ENCODING "clwb %[p]" -#elif defined(HAVE_AS_XSAVEOPT) -# define CLWB_ENCODING "data16 xsaveopt %[p]" /* clwb */ -#else -# define CLWB_ENCODING ".byte 0x66, 0x0f, 0xae, 0x30" /* clwb (%%rax) */ -#endif - -#define BASE_INPUT(addr) [p] "m" (*(const char *)(addr)) -#if defined(HAVE_AS_CLWB) || defined(HAVE_AS_XSAVEOPT) -# define INPUT BASE_INPUT -#else -# define INPUT(addr) "a" (addr), BASE_INPUT(addr) -#endif - /* - * Note regarding the use of NOP_DS_PREFIX: it's faster to do a clflush - * + prefix than a clflush + nop, and hence the prefix is added instead - * of letting the alternative framework fill the gap by appending nops. - */ - alternative_io_2(".byte " __stringify(NOP_DS_PREFIX) "; clflush %[p]", - "data16 clflush %[p]", /* clflushopt */ - X86_FEATURE_CLFLUSHOPT, - CLWB_ENCODING, - X86_FEATURE_CLWB, /* no outputs */, - INPUT(addr)); -#undef INPUT -#undef BASE_INPUT -#undef CLWB_ENCODING - - alternative_2("", "sfence", X86_FEATURE_CLFLUSHOPT, - "sfence", X86_FEATURE_CLWB); -} - /* Allocate page table, return its machine address */ uint64_t alloc_pgtable_maddr(unsigned long npages, nodeid_t node) { @@ -268,8 +220,7 @@ uint64_t alloc_pgtable_maddr(unsigned lo clear_page(vaddr); - if ( (iommu_ops.init ? &iommu_ops : &vtd_ops)->sync_cache ) - sync_cache(vaddr, PAGE_SIZE); + iommu_sync_cache(vaddr, PAGE_SIZE); unmap_domain_page(vaddr); cur_pg++; } @@ -1295,7 +1246,7 @@ int __init iommu_alloc(struct acpi_drhd_ iommu->nr_pt_levels = agaw_to_level(agaw); if ( !ecap_coherent(iommu->ecap) ) - vtd_ops.sync_cache = sync_cache; + iommu_non_coherent = true; /* allocate domain id bitmap */ nr_dom = cap_ndoms(iommu->cap); --- a/xen/drivers/passthrough/x86/iommu.c +++ b/xen/drivers/passthrough/x86/iommu.c @@ -28,6 +28,7 @@ const struct iommu_init_ops *__initdata iommu_init_ops; struct iommu_ops __read_mostly iommu_ops; +bool __read_mostly iommu_non_coherent; enum iommu_intremap __read_mostly iommu_intremap = iommu_intremap_full; @@ -435,8 +436,7 @@ struct page_info *iommu_alloc_pgtable(st p = __map_domain_page(pg); clear_page(p); - if ( hd->platform_ops->sync_cache ) - iommu_vcall(hd->platform_ops, sync_cache, p, PAGE_SIZE); + iommu_sync_cache(p, PAGE_SIZE); unmap_domain_page(p); --- a/xen/include/asm-x86/cache.h +++ b/xen/include/asm-x86/cache.h @@ -11,4 +11,10 @@ #define __read_mostly __section(".data.read_mostly") +#ifndef __ASSEMBLY__ + +void sync_cache(const void *addr, unsigned int size); + +#endif + #endif --- a/xen/include/asm-x86/iommu.h +++ b/xen/include/asm-x86/iommu.h @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -134,12 +135,13 @@ extern bool untrusted_msi; int pi_update_irte(const struct pi_desc *pi_desc, const struct pirq *pirq, const uint8_t gvec); -#define iommu_sync_cache(addr, size) ({ \ - const struct iommu_ops *ops = iommu_get_ops(); \ - \ - if ( ops->sync_cache ) \ - iommu_vcall(ops, sync_cache, addr, size); \ -}) +extern bool iommu_non_coherent; + +static inline void iommu_sync_cache(const void *addr, unsigned int size) +{ + if ( iommu_non_coherent ) + sync_cache(addr, size); +} int __must_check iommu_free_pgtables(struct domain *d); struct page_info *__must_check iommu_alloc_pgtable(struct domain *d); --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -268,7 +268,6 @@ struct iommu_ops { int (*setup_hpet_msi)(struct msi_desc *); int (*adjust_irq_affinities)(void); - void (*sync_cache)(const void *addr, unsigned int size); void (*clear_root_pgtable)(struct domain *d); int (*update_ire_from_msi)(struct msi_desc *msi_desc, struct msi_msg *msg); #endif /* CONFIG_X86 */ --- a/xen/drivers/passthrough/vtd/extern.h +++ b/xen/drivers/passthrough/vtd/extern.h @@ -76,7 +76,6 @@ int __must_check qinval_device_iotlb_syn struct pci_dev *pdev, u16 did, u16 size, u64 addr); -unsigned int get_cache_line_size(void); void flush_all_cache(void); uint64_t alloc_pgtable_maddr(unsigned long npages, nodeid_t node); --- a/xen/drivers/passthrough/vtd/x86/vtd.c +++ b/xen/drivers/passthrough/vtd/x86/vtd.c @@ -47,11 +47,6 @@ void unmap_vtd_domain_page(const void *v unmap_domain_page(va); } -unsigned int get_cache_line_size(void) -{ - return ((cpuid_ebx(1) >> 8) & 0xff) * 8; -} - void flush_all_cache() { wbinvd();