@@ -263,6 +263,7 @@ int libxl_cpuid_parse_config(libxl_cpuid
{"clzero", 0x80000008, NA, CPUID_REG_EBX, 0, 1},
{"rstr-fp-err-ptrs", 0x80000008, NA, CPUID_REG_EBX, 2, 1},
{"rdpru", 0x80000008, NA, CPUID_REG_EBX, 4, 1},
+ {"mcommit", 0x80000008, NA, CPUID_REG_EBX, 8, 1},
{"wbnoinvd", 0x80000008, NA, CPUID_REG_EBX, 9, 1},
{"ibpb", 0x80000008, NA, CPUID_REG_EBX, 12, 1},
{"ppin", 0x80000008, NA, CPUID_REG_EBX, 23, 1},
@@ -150,7 +150,7 @@ static const char *const str_e8b[32] =
[ 4] = "rdpru",
- /* [ 8] */ [ 9] = "wbnoinvd",
+ [ 8] = "mcommit", [ 9] = "wbnoinvd",
[12] = "ibpb",
@@ -798,6 +798,9 @@ static void init_amd(struct cpuinfo_x86
wrmsr(MSR_K7_HWCR, l, h);
}
+ if (cpu_has(c, X86_FEATURE_MCOMMIT))
+ write_efer(read_efer() | EFER_MCOMMIT);
+
/* Prevent TSC drift in non single-processor, single-core platforms. */
if ((smp_processor_id() == 1) && !cpu_has(c, X86_FEATURE_ITSC))
disable_c1_ramping();
@@ -1889,6 +1889,7 @@ amd_like(const struct x86_emulate_ctxt *
#define vcpu_has_fma4() (ctxt->cpuid->extd.fma4)
#define vcpu_has_tbm() (ctxt->cpuid->extd.tbm)
#define vcpu_has_clzero() (ctxt->cpuid->extd.clzero)
+#define vcpu_has_mcommit() (ctxt->cpuid->extd.mcommit)
#define vcpu_has_rdpru() (ctxt->cpuid->extd.rdpru)
#define vcpu_has_wbnoinvd() (ctxt->cpuid->extd.wbnoinvd)
@@ -5718,6 +5719,28 @@ x86_emulate(
_regs.r(cx) = (uint32_t)msr_val;
goto rdtsc;
+ case 0xfa: /* monitorx / mcommit */
+ if ( vex.pfx == vex_f3 )
+ {
+ bool cf;
+
+ host_and_vcpu_must_have(mcommit);
+ if ( !ops->read_msr ||
+ ops->read_msr(MSR_EFER, &msr_val, ctxt) != X86EMUL_OKAY )
+ msr_val = 0;
+ generate_exception_if(!(msr_val & EFER_MCOMMIT), EXC_UD);
+ memcpy(get_stub(stub),
+ ((uint8_t[]){ 0xf3, 0x0f, 0x01, 0xfa, 0xc3 }), 5);
+ _regs.eflags &= ~EFLAGS_MASK;
+ invoke_stub("", ASM_FLAG_OUT(, "setc %[cf]"),
+ [cf] ASM_FLAG_OUT("=@ccc", "=qm") (cf) : "i" (0));
+ if ( cf )
+ _regs.eflags |= X86_EFLAGS_CF;
+ put_stub(stub);
+ goto done;
+ }
+ goto unrecognized_insn;
+
case 0xfc: /* clzero */
{
unsigned long zero = 0;
@@ -133,6 +133,9 @@
#define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)
#define cpu_has_serialize boot_cpu_has(X86_FEATURE_SERIALIZE)
+/* CPUID level 0x80000008.ebx */
+#define cpu_has_mcommit boot_cpu_has(X86_FEATURE_MCOMMIT)
+
/* CPUID level 0x00000007:1.eax */
#define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16)
@@ -78,6 +78,11 @@ enum GenericIntercept2bits
GENERAL2_INTERCEPT_RDPRU = 1 << 14,
};
+/* general 3 intercepts */
+enum GenericIntercept3bits
+{
+ GENERAL3_INTERCEPT_MCOMMIT = 1 << 3,
+};
/* control register intercepts */
enum CRInterceptBits
@@ -300,6 +305,7 @@ enum VMEXIT_EXITCODE
VMEXIT_MWAIT_CONDITIONAL= 140, /* 0x8c */
VMEXIT_XSETBV = 141, /* 0x8d */
VMEXIT_RDPRU = 142, /* 0x8e */
+ VMEXIT_MCOMMIT = 163, /* 0xa3 */
VMEXIT_NPF = 1024, /* 0x400, nested paging fault */
VMEXIT_INVALID = -1
};
@@ -414,7 +420,8 @@ struct vmcb_struct {
u32 _exception_intercepts; /* offset 0x08 - cleanbit 0 */
u32 _general1_intercepts; /* offset 0x0C - cleanbit 0 */
u32 _general2_intercepts; /* offset 0x10 - cleanbit 0 */
- u32 res01[10];
+ u32 _general3_intercepts; /* offset 0x14 - cleanbit 0 */
+ u32 res01[9];
u16 _pause_filter_thresh; /* offset 0x3C - cleanbit 0 */
u16 _pause_filter_count; /* offset 0x3E - cleanbit 0 */
u64 _iopm_base_pa; /* offset 0x40 - cleanbit 1 */
@@ -611,6 +618,7 @@ VMCB_ACCESSORS(dr_intercepts, intercepts
VMCB_ACCESSORS(exception_intercepts, intercepts)
VMCB_ACCESSORS(general1_intercepts, intercepts)
VMCB_ACCESSORS(general2_intercepts, intercepts)
+VMCB_ACCESSORS(general3_intercepts, intercepts)
VMCB_ACCESSORS(pause_filter_count, intercepts)
VMCB_ACCESSORS(pause_filter_thresh, intercepts)
VMCB_ACCESSORS(tsc_offset, intercepts)
@@ -88,6 +88,7 @@
#define _EFER_NX 11 /* No execute enable */
#define _EFER_SVME 12 /* AMD: SVM enable */
#define _EFER_FFXSE 14 /* AMD: Fast FXSAVE/FXRSTOR enable */
+#define _EFER_MCOMMIT 17 /* AMD: MCOMMIT insn enable */
#define EFER_SCE (1<<_EFER_SCE)
#define EFER_LME (1<<_EFER_LME)
@@ -95,9 +96,10 @@
#define EFER_NX (1<<_EFER_NX)
#define EFER_SVME (1<<_EFER_SVME)
#define EFER_FFXSE (1<<_EFER_FFXSE)
+#define EFER_MCOMMIT (1<<_EFER_MCOMMIT)
#define EFER_KNOWN_MASK (EFER_SCE | EFER_LME | EFER_LMA | EFER_NX | \
- EFER_SVME | EFER_FFXSE)
+ EFER_SVME | EFER_FFXSE | EFER_MCOMMIT)
/* Intel MSRs. Some also available on other CPUs */
#define MSR_IA32_PERFCTR0 0x000000c1
@@ -250,6 +250,7 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /
XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */
XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always saves/restores FPU Error pointers */
XEN_CPUFEATURE(RDPRU, 8*32+ 4) /*A RDPRU instruction */
+XEN_CPUFEATURE(MCOMMIT, 8*32+ 8) /*A MCOMMIT instruction */
XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */
XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */
XEN_CPUFEATURE(AMD_PPIN, 8*32+23) /* Protected Processor Inventory Number */
The dependency on a new EFER bit implies that we need to set that bit ourselves in order to be able to successfully invoke the insn. Also once again introduce the SVM related constants at this occasion. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- RFC: The exact meaning of the PM stating "any errors encountered by those stores have been signaled to associated error logging resources" is unclear. Depending on what this entails, blindly enabling EFER.MCOMMIT may not be a good idea. Hence the RFC. --- v6: Re-base. v5: Re-base. v4: New.