diff mbox series

[XEN,v2] arm/gic: add missing parameter names and uniform function declarations

Message ID f22122c2b82f704dff17a455877c213940b54cc7.1697633691.git.federico.serafini@bugseng.com (mailing list archive)
State New, archived
Headers show
Series [XEN,v2] arm/gic: add missing parameter names and uniform function declarations | expand

Commit Message

Federico Serafini Oct. 18, 2023, 1:14 p.m. UTC 
Add missing parameter names and remove inconsistencies between GICv3
and GICv2. No functional change.

Signed-off-by: Federico Serafini <federico.serafini@bugseng.com>
---
Changes in v2:
- switched parameter names of gicv3_write_lr().
---
 xen/arch/arm/gic-v3.c          | 22 +++++++++++-----------
 xen/arch/arm/include/asm/gic.h | 12 ++++++------
 2 files changed, 17 insertions(+), 17 deletions(-)

Comments

Stefano Stabellini Oct. 19, 2023, 12:38 a.m. UTC | #1 
On Wed, 18 Oct 2023, Federico Serafini wrote:
> Add missing parameter names and remove inconsistencies between GICv3
> and GICv2. No functional change.
> 
> Signed-off-by: Federico Serafini <federico.serafini@bugseng.com>

Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
diff mbox series

Patch

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 95e4f020fe..172ff8c005 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -1086,29 +1086,29 @@  static void gicv3_read_lr(int lr, struct gic_lr *lr_reg)
     }
 }
 
-static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr)
+static void gicv3_write_lr(int lr, const struct gic_lr *lr_reg)
 {
     uint64_t lrv = 0;
     const enum gic_version vgic_version = current->domain->arch.vgic.version;
 
 
-    lrv = ( ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK)  << ICH_LR_VIRTUAL_SHIFT) |
-        ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT) );
+    lrv = ( ((u64)(lr_reg->virq & ICH_LR_VIRTUAL_MASK)  << ICH_LR_VIRTUAL_SHIFT) |
+        ((u64)(lr_reg->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT) );
 
-    if ( lr->active )
+    if ( lr_reg->active )
         lrv |= ICH_LR_STATE_ACTIVE;
 
-    if ( lr->pending )
+    if ( lr_reg->pending )
         lrv |= ICH_LR_STATE_PENDING;
 
-    if ( lr->hw_status )
+    if ( lr_reg->hw_status )
     {
         lrv |= ICH_LR_HW;
-        lrv |= (uint64_t)lr->hw.pirq << ICH_LR_PHYSICAL_SHIFT;
+        lrv |= (uint64_t)lr_reg->hw.pirq << ICH_LR_PHYSICAL_SHIFT;
     }
     else
     {
-        if ( lr->virt.eoi )
+        if ( lr_reg->virt.eoi )
             lrv |= ICH_LR_MAINTENANCE_IRQ;
         /* Source is only set in GICv2 compatible mode */
         if ( vgic_version == GIC_V2 )
@@ -1117,8 +1117,8 @@  static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr)
              * Source is only valid for SGIs, the caller should make
              * sure the field virt.source is always 0 for non-SGI.
              */
-            ASSERT(!lr->virt.source || lr->virq < NR_GIC_SGI);
-            lrv |= (uint64_t)lr->virt.source << ICH_LR_CPUID_SHIFT;
+            ASSERT(!lr_reg->virt.source || lr_reg->virq < NR_GIC_SGI);
+            lrv |= (uint64_t)lr_reg->virt.source << ICH_LR_CPUID_SHIFT;
         }
     }
 
@@ -1129,7 +1129,7 @@  static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr)
     if ( vgic_version == GIC_V3 )
         lrv |= ICH_LR_GRP1;
 
-    gicv3_ich_write_lr(lr_reg, lrv);
+    gicv3_ich_write_lr(lr, lrv);
 }
 
 static void gicv3_hcr_status(uint32_t flag, bool status)
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h
index f1ef347edc..03f209529b 100644
--- a/xen/arch/arm/include/asm/gic.h
+++ b/xen/arch/arm/include/asm/gic.h
@@ -246,7 +246,7 @@  void gic_set_irq_type(struct irq_desc *desc, unsigned int type);
 
 /* Program the GIC to route an interrupt */
 extern void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority);
-extern int gic_route_irq_to_guest(struct domain *, unsigned int virq,
+extern int gic_route_irq_to_guest(struct domain *d, unsigned int virq,
                                   struct irq_desc *desc,
                                   unsigned int priority);
 
@@ -330,11 +330,11 @@  struct gic_hw_operations {
     /* Initialize the GIC and the boot CPU */
     int (*init)(void);
     /* Save GIC registers */
-    void (*save_state)(struct vcpu *);
+    void (*save_state)(struct vcpu *v);
     /* Restore GIC registers */
-    void (*restore_state)(const struct vcpu *);
+    void (*restore_state)(const struct vcpu *v);
     /* Dump GIC LR register information */
-    void (*dump_state)(const struct vcpu *);
+    void (*dump_state)(const struct vcpu *v);
 
     /* hw_irq_controller to enable/disable/eoi host irq */
     hw_irq_controller *gic_host_irq_type;
@@ -369,9 +369,9 @@  struct gic_hw_operations {
     /* Clear LR register */
     void (*clear_lr)(int lr);
     /* Read LR register and populate gic_lr structure */
-    void (*read_lr)(int lr, struct gic_lr *);
+    void (*read_lr)(int lr, struct gic_lr *lr_reg);
     /* Write LR register from gic_lr structure */
-    void (*write_lr)(int lr, const struct gic_lr *);
+    void (*write_lr)(int lr, const struct gic_lr *lr_reg);
     /* Read VMCR priority */
     unsigned int (*read_vmcr_priority)(void);
     /* Read APRn register */