diff mbox series

[RFC,06/22] x86/PMUv1: limit arch PMCs to 4 for non-Dom0

Message ID fc28de1f8d0558829ae902cc2a76063ec31815df.1698261255.git.edwin.torok@cloud.com (mailing list archive)
State New, archived
Headers show
Series vPMU bugfixes and support for PMUv5 | expand

Commit Message

Edwin Torok Oct. 25, 2023, 7:29 p.m. UTC 
From: Edwin Török <edvin.torok@citrix.com>

Only PERFEVTSEL{0-3} are architectural MSRs and Thread scoped.

PERFEVTSEL{4-7} are Core scoped, and we cannot allow using them if more
than 1 guest can attempt to modify them: if they program them with
different events (quite likely when multiplexing) then one of the VMs
would sample the wrong PMCs.

For now only allow this when Dom0 is the only one using the PMU, i.e. in
vpmu mode `all`.

We could also allow this when sched_gran >= SCHED_GRAN_core, but we
don't have access to the cpupool here.

There is some indication that this was causing bugs, e.g.
`pcm` mentions about a bug with perf counters beyond 3 on AWS:
https://github.com/opcm/pcm/commit/02f3b00f304401c723131372e09b71798df613ff

Backport: 4.0+

Signed-off-by: Edwin Török <edvin.torok@citrix.com>
---
 xen/arch/x86/cpu/vpmu_intel.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
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Patch

diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
index 9602728f1b..ec9ab01fde 100644
--- a/xen/arch/x86/cpu/vpmu_intel.c
+++ b/xen/arch/x86/cpu/vpmu_intel.c
@@ -926,6 +926,16 @@  const struct arch_vpmu_ops *__init core2_vpmu_init(void)
     }
 
     arch_pmc_cnt = core2_get_arch_pmc_count();
+    if ( arch_pmc_cnt > 4 &&
+         vpmu_mode != XENPMU_MODE_ALL )
+    {
+        /* Architectural PMCs 0-3 are Thread scoped, but 4+ are Core scoped.
+         * We can only allow using them if we know that we have at most one guest using a PMU
+         * on all siblings threads on a core. */
+        printk(XENLOG_INFO "VPMU: limiting architectural PMCs to 4\n");
+        arch_pmc_cnt = 4;
+    }
+
     fixed_pmc_cnt = core2_get_fixed_pmc_count();
 
     if ( cpu_has_pdcm )