From patchwork Wed Dec 20 11:03:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Federico Serafini X-Patchwork-Id: 13499978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52028C4706F for ; Wed, 20 Dec 2023 11:03:34 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.657633.1026628 (Exim 4.92) (envelope-from ) id 1rFuME-0005CK-2j; Wed, 20 Dec 2023 11:03:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 657633.1026628; Wed, 20 Dec 2023 11:03:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rFuMD-0005Ba-T5; Wed, 20 Dec 2023 11:03:21 +0000 Received: by outflank-mailman (input) for mailman id 657633; Wed, 20 Dec 2023 11:03:20 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rFuMC-00054g-JY for xen-devel@lists.xenproject.org; Wed, 20 Dec 2023 11:03:20 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 61969488-9f27-11ee-9b0f-b553b5be7939; Wed, 20 Dec 2023 12:03:18 +0100 (CET) Received: from Dell.bugseng.com (unknown [37.161.218.228]) by support.bugseng.com (Postfix) with ESMTPSA id 6169E4EE0C99; Wed, 20 Dec 2023 12:03:17 +0100 (CET) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 61969488-9f27-11ee-9b0f-b553b5be7939 From: Federico Serafini To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Federico Serafini , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [XEN PATCH 1/7] xen/arm: gic-v3: address violations of MISRA C:2012 Rule 16.3 Date: Wed, 20 Dec 2023 12:03:01 +0100 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Add the pseudo-keyword fallthrough to meet the requirements to deviate Rule 16.3 ("An unconditional `break' statement shall terminate every switch-clause"). No functional change. Signed-off-by: Federico Serafini Acked-by: Julien Grall --- xen/arch/arm/gic-v3.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 18289cd645..bf0e5c1b75 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -65,34 +65,49 @@ static inline void gicv3_save_lrs(struct vcpu *v) { case 16: v->arch.gic.v3.lr[15] = READ_SYSREG_LR(15); + fallthrough; case 15: v->arch.gic.v3.lr[14] = READ_SYSREG_LR(14); + fallthrough; case 14: v->arch.gic.v3.lr[13] = READ_SYSREG_LR(13); + fallthrough; case 13: v->arch.gic.v3.lr[12] = READ_SYSREG_LR(12); + fallthrough; case 12: v->arch.gic.v3.lr[11] = READ_SYSREG_LR(11); + fallthrough; case 11: v->arch.gic.v3.lr[10] = READ_SYSREG_LR(10); + fallthrough; case 10: v->arch.gic.v3.lr[9] = READ_SYSREG_LR(9); + fallthrough; case 9: v->arch.gic.v3.lr[8] = READ_SYSREG_LR(8); + fallthrough; case 8: v->arch.gic.v3.lr[7] = READ_SYSREG_LR(7); + fallthrough; case 7: v->arch.gic.v3.lr[6] = READ_SYSREG_LR(6); + fallthrough; case 6: v->arch.gic.v3.lr[5] = READ_SYSREG_LR(5); + fallthrough; case 5: v->arch.gic.v3.lr[4] = READ_SYSREG_LR(4); + fallthrough; case 4: v->arch.gic.v3.lr[3] = READ_SYSREG_LR(3); + fallthrough; case 3: v->arch.gic.v3.lr[2] = READ_SYSREG_LR(2); + fallthrough; case 2: v->arch.gic.v3.lr[1] = READ_SYSREG_LR(1); + fallthrough; case 1: v->arch.gic.v3.lr[0] = READ_SYSREG_LR(0); break; @@ -112,34 +127,49 @@ static inline void gicv3_restore_lrs(const struct vcpu *v) { case 16: WRITE_SYSREG_LR(v->arch.gic.v3.lr[15], 15); + fallthrough; case 15: WRITE_SYSREG_LR(v->arch.gic.v3.lr[14], 14); + fallthrough; case 14: WRITE_SYSREG_LR(v->arch.gic.v3.lr[13], 13); + fallthrough; case 13: WRITE_SYSREG_LR(v->arch.gic.v3.lr[12], 12); + fallthrough; case 12: WRITE_SYSREG_LR(v->arch.gic.v3.lr[11], 11); + fallthrough; case 11: WRITE_SYSREG_LR(v->arch.gic.v3.lr[10], 10); + fallthrough; case 10: WRITE_SYSREG_LR(v->arch.gic.v3.lr[9], 9); + fallthrough; case 9: WRITE_SYSREG_LR(v->arch.gic.v3.lr[8], 8); + fallthrough; case 8: WRITE_SYSREG_LR(v->arch.gic.v3.lr[7], 7); + fallthrough; case 7: WRITE_SYSREG_LR(v->arch.gic.v3.lr[6], 6); + fallthrough; case 6: WRITE_SYSREG_LR(v->arch.gic.v3.lr[5], 5); + fallthrough; case 5: WRITE_SYSREG_LR(v->arch.gic.v3.lr[4], 4); + fallthrough; case 4: WRITE_SYSREG_LR(v->arch.gic.v3.lr[3], 3); + fallthrough; case 3: WRITE_SYSREG_LR(v->arch.gic.v3.lr[2], 2); + fallthrough; case 2: WRITE_SYSREG_LR(v->arch.gic.v3.lr[1], 1); + fallthrough; case 1: WRITE_SYSREG_LR(v->arch.gic.v3.lr[0], 0); break;