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[148.88.224.78]) by smtp.gmail.com with ESMTPSA id g8sm68134975wro.77.2019.04.12.10.25.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Apr 2019 10:25:47 -0700 (PDT) Date: Fri, 12 Apr 2019 18:25:46 +0100 From: Willy Wolff To: Rob Herring , Mark Rutland , Kukjin Kim , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM: dts: exynos: add CCI-400 PMU nodes support to Exynos542x SoCs Message-ID: <20190412172545.fkxnpnymhcw7xncc@macpro-scc.lancs.ac.uk> MIME-Version: 1.0 Content-Disposition: inline User-Agent: NeoMutt/20170113 (1.7.2) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190412_102549_512827_E2E00911 X-CRM114-Status: GOOD ( 12.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add device tree entries for PMU of ARM CCI-400. $ sudo ./perf stat -a -C 0 -e CCI_400/config=0xff,name=cycles/ sleep 1 Performance counter stats for 'system wide': 420,303,619 cycles 1.019058775 seconds time elapsed Tested on Odroid-xu3 and 4. Signed-off-by: Willy Wolff --- arch/arm/boot/dts/exynos5420.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index aaff15880761..be58650aca35 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -158,7 +158,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x10d20000 0x1000>; - ranges = <0x0 0x10d20000 0x6000>; + ranges = <0x0 0x10d20000 0x10000>; cci_control0: slave-if@4000 { compatible = "arm,cci-400-ctrl-if"; @@ -170,6 +170,16 @@ interface-type = "ace"; reg = <0x5000 0x1000>; }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r0"; + reg = <0x9000 0x5000>; + interrupts = <0 105 4>, + <0 101 4>, + <0 102 4>, + <0 103 4>, + <0 104 4>; + }; }; clock: clock-controller@10010000 {